| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 43 unsigned Opc = MI->getOpcode();
45 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
65 unsigned Opc = MI->getOpcode();
67 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164))
[all...] |
| Mips16InstrInfo.cpp | 65 unsigned Opc = 0;
69 Opc = Mips::MoveR3216;
72 Opc = Mips::Move32R16;
75 Opc = Mips::Mfhi16, SrcReg = 0;
79 Opc = Mips::Mflo16, SrcReg = 0;
82 assert(Opc && "Cannot copy registers");
84 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
102 unsigned Opc = 0;
104 Opc = Mips::SwRxSpImmX16;
105 assert(Opc && "Register class not handled!")
[all...] |
| MipsAnalyzeImmediate.h | 20 unsigned Opc, ImmOpnd;
21 Inst(unsigned Opc, unsigned ImmOpnd);
|
| MipsSEInstrInfo.h | 67 unsigned getOppositeBranchOpc(unsigned Opc) const override;
81 unsigned getAnalyzableBrOpc(unsigned Opc) const override;
87 std::pair<bool, bool> compareOpndSize(unsigned Opc,
|
| Mips16InstrInfo.h | 67 unsigned getOppositeBranchOpc(unsigned Opc) const override;
109 unsigned getAnalyzableBrOpc(unsigned Opc) const override;
112 unsigned Opc) const;
|
| MipsInstrInfo.h | 84 virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
135 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
137 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
|
| Mips16ISelDAGToDAG.h | 26 std::pair<SDNode*, SDNode*> selectMULT(SDNode *N, unsigned Opc, SDLoc DL,
|
| MipsAnalyzeImmediate.cpp | 15 MipsAnalyzeImmediate::Inst::Inst(unsigned O, unsigned I) : Opc(O), ImmOpnd(I) {}
89 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) ||
90 (Seq[1].Opc != SLL) || (Seq[1].ImmOpnd < 16))
101 Seq[0].Opc = LUi;
|
| Mips16ISelDAGToDAG.cpp | 47 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, SDLoc DL, EVT Ty,
50 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
262 unsigned Opc = InFlag.getOpcode(); (void)Opc;
263 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
264 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 82 int Opc = MI->getOpcode();
83 if (Opc == Hexagon::S2_storerb_pci_pseudo ||
84 Opc == Hexagon::S2_storerh_pci_pseudo ||
85 Opc == Hexagon::S2_storeri_pci_pseudo ||
86 Opc == Hexagon::S2_storerd_pci_pseudo ||
87 Opc == Hexagon::S2_storerf_pci_pseudo) {
89 if (Opc == Hexagon::S2_storerd_pci_pseudo)
91 else if (Opc == Hexagon::S2_storeri_pci_pseudo)
93 else if (Opc == Hexagon::S2_storerh_pci_pseudo)
95 else if (Opc == Hexagon::S2_storerf_pci_pseudo
[all...] |
| HexagonCFGOptimizer.cpp | 58 static bool IsConditionalBranch(int Opc) {
59 return (Opc == Hexagon::J2_jumpt) || (Opc == Hexagon::J2_jumpf)
60 || (Opc == Hexagon::J2_jumptnewpt) || (Opc == Hexagon::J2_jumpfnewpt);
64 static bool IsUnconditionalJump(int Opc) {
65 return (Opc == Hexagon::J2_jump);
111 int Opc = MI->getOpcode();
112 if (IsConditionalBranch(Opc)) {
|
| HexagonSplitConst32AndConst64.cpp | 90 int Opc = MI->getOpcode();
91 if (Opc == Hexagon::CONST32_Int_Real &&
106 else if (Opc == Hexagon::CONST32_Int_Real ||
107 Opc == Hexagon::CONST32_Float_Real) {
113 if (Opc == Hexagon::CONST32_Float_Real) {
125 else if (Opc == Hexagon::CONST64_Int_Real ||
126 Opc == Hexagon::CONST64_Float_Real) {
132 if (Opc == Hexagon::CONST64_Float_Real) {
|
| HexagonGenPredicate.cpp | 94 unsigned getPredForm(unsigned Opc);
96 bool isScalarCmp(unsigned Opc);
120 unsigned HexagonGenPredicate::getPredForm(unsigned Opc) {
123 switch (Opc) {
166 unsigned Opc = MI->getOpcode();
167 if (getPredForm(Opc) != 0)
174 switch (Opc) {
190 unsigned Opc = MI->getOpcode();
191 switch (Opc) {
238 unsigned Opc = DefI->getOpcode()
[all...] |
| HexagonGenMux.cpp | 91 bool isCondTransfer(unsigned Opc) const;
121 unsigned Opc = MI->getOpcode();
122 const MCInstrDesc &D = HII->get(Opc);
159 bool HexagonGenMux::isCondTransfer(unsigned Opc) const {
160 switch (Opc) {
202 unsigned Opc = MI->getOpcode();
203 if (!isCondTransfer(Opc))
212 bool IfTrue = HII->isPredicatedTrue(Opc);
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 105 // Return the non-pre/post incrementing version of 'Opc'. Return 0
107 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
416 bool isUncondBranchOpcode(int Opc) {
417 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
421 bool isCondBranchOpcode(int Opc) {
422 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc
[all...] |
| ARMInstrInfo.h | 31 // Return the non-pre/post incrementing version of 'Opc'. Return 0
33 unsigned getUnindexedOpcode(unsigned Opc) const override;
|
| Thumb1InstrInfo.h | 31 // Return the non-pre/post incrementing version of 'Opc'. Return 0
33 unsigned getUnindexedOpcode(unsigned Opc) const override;
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 611 unsigned Opc;
615 Opc = TM.is64Bit() ? NVPTX::cvta_global_yes_64 : NVPTX::cvta_global_yes;
618 Opc = TM.is64Bit() ? NVPTX::cvta_shared_yes_64 : NVPTX::cvta_shared_yes;
621 Opc = TM.is64Bit() ? NVPTX::cvta_const_yes_64 : NVPTX::cvta_const_yes;
624 Opc = TM.is64Bit() ? NVPTX::cvta_local_yes_64 : NVPTX::cvta_local_yes;
627 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
632 unsigned Opc;
636 Opc = TM.is64Bit() ? NVPTX::cvta_to_global_yes_64
640 Opc = TM.is64Bit() ? NVPTX::cvta_to_shared_yes_64
644 Opc
[all...] |
| /external/llvm/include/llvm/IR/ |
| AutoUpgrade.h | 55 Instruction *UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy,
61 Value *UpgradeBitCastExpr(unsigned Opc, Constant *C, Type *DestTy);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 113 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
452 unsigned Opc;
476 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
479 Opc = (IsZExt ?
484 Opc = (IsZExt ?
487 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
491 Opc = PPC::LD;
497 Opc = PPC::LFS;
500 Opc = FP64LoadOpc
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ConditionOptimizer.cpp | 199 static int getComplementOpc(int Opc) {
200 switch (Opc) {
226 unsigned Opc = CmpMI->getOpcode();
230 bool Negative = (Opc == AArch64::ADDSWri || Opc == AArch64::ADDSXri);
245 Opc = getComplementOpc(Opc);
248 return CmpInfo(NewImm, Opc, getAdjustedCmp(Cmp));
255 unsigned Opc;
257 std::tie(Imm, Opc, Cmp) = Info
[all...] |
| AArch64ConditionalCompares.cpp | 580 unsigned Opc = 0;
584 Opc = AArch64::SUBSWri;
588 Opc = AArch64::SUBSXri;
593 const MCInstrDesc &MCID = TII->get(Opc);
612 unsigned Opc = 0;
618 case AArch64::SUBSWri: Opc = AArch64::CCMPWi; break;
619 case AArch64::SUBSWrr: Opc = AArch64::CCMPWr; break;
620 case AArch64::SUBSXri: Opc = AArch64::CCMPXi; break;
621 case AArch64::SUBSXrr: Opc = AArch64::CCMPXr; break;
622 case AArch64::ADDSWri: Opc = AArch64::CCMNWi; break
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 96 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
128 bool X86SelectFPExtOrFPTrunc(const Instruction *I, unsigned Opc,
351 unsigned Opc = 0;
357 Opc = X86::MOV8rm;
361 Opc = X86::MOV16rm;
365 Opc = X86::MOV32rm;
370 Opc = X86::MOV64rm;
375 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
378 Opc = X86::LD_Fp32m;
384 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SILoadStoreOptimizer.cpp | 227 unsigned Opc = (EltSize == 4) ? AMDGPU::DS_READ2_B32 : AMDGPU::DS_READ2_B64;
235 Opc = (EltSize == 4) ? AMDGPU::DS_READ2ST64_B32 : AMDGPU::DS_READ2ST64_B64;
242 const MCInstrDesc &Read2Desc = TII->get(Opc);
323 unsigned Opc = (EltSize == 4) ? AMDGPU::DS_WRITE2_B32 : AMDGPU::DS_WRITE2_B64;
331 Opc = (EltSize == 4) ? AMDGPU::DS_WRITE2ST64_B32 : AMDGPU::DS_WRITE2ST64_B64;
338 const MCInstrDesc &Write2Desc = TII->get(Opc);
394 unsigned Opc = MI.getOpcode();
395 if (Opc == AMDGPU::DS_READ_B32 || Opc == AMDGPU::DS_READ_B64) {
396 unsigned Size = (Opc == AMDGPU::DS_READ_B64) ? 8 : 4
[all...] |
| /external/llvm/utils/TableGen/ |
| FixedLenDecoderEmitter.cpp | 414 void SingletonExists(unsigned Opc) const;
432 unsigned Opc) const;
434 bool doesOpcodeNeedPredicate(unsigned Opc) const;
437 unsigned Opc) const;
440 unsigned Opc) const;
444 unsigned Opc) const;
454 void emitDecoder(raw_ostream &OS, unsigned Indentation, unsigned Opc,
456 unsigned getDecoderIndex(DecoderSet &Decoders, unsigned Opc,
795 unsigned Opc = decodeULEB128(Buffer);
809 << NumberedInstructions->at(Opc)->TheDef->getName() << "\n"
[all...] |
