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    Searched refs:RegIdx (Results 1 - 13 of 13) sorted by null

  /external/llvm/lib/CodeGen/
SplitKit.h 277 /// intervals. Given a pair (RegIdx, ParentVNI->id), Values contains:
279 /// 1. No entry - the value is not mapped to Edit.get(RegIdx).
281 /// Edit.get(RegIdx). Each value is represented by a minimal live range at
283 /// of RegIdx in RegAssign.
295 /// getLRCalc - Return the LRCalc to use for RegIdx. In spill mode, the
298 LiveRangeCalc &getLRCalc(unsigned RegIdx) {
299 return LRCalc[SpillMode != SM_Partition && RegIdx != 0];
302 /// defValue - define a value in RegIdx from ParentVNI at Idx.
307 VNInfo *defValue(unsigned RegIdx, const VNInfo *ParentVNI, SlotIndex Idx);
309 /// forceRecompute - Force the live range of ParentVNI in RegIdx to b
    [all...]
SplitKit.cpp 362 VNInfo *SplitEditor::defValue(unsigned RegIdx,
368 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
375 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id),
378 // This was the first time (RegIdx, ParentVNI) was mapped.
398 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo *ParentVNI) {
400 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->id)];
413 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
419 VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
426 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx));
429 // so always begin RegIdx 0 early and all others late
    [all...]
LiveVariables.cpp 85 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
86 assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
88 VirtRegInfo.grow(RegIdx);
89 return VirtRegInfo[RegIdx];
  /external/llvm/lib/Target/ARM/
ARMCallingConv.h 210 unsigned RegIdx = State.getFirstUnallocated(RegList);
215 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size())
216 State.AllocateReg(RegList[RegIdx++]);
251 unsigned RegIdx = State.getFirstUnallocated(RegList);
253 if (RegIdx >= RegList.size())
256 It.convertToReg(State.AllocateReg(RegList[RegIdx++]));
ARMISelLowering.cpp     [all...]
  /external/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp 633 struct RegIdxOp RegIdx;
647 Op->RegIdx.Index = Index;
648 Op->RegIdx.RegInfo = RegInfo;
649 Op->RegIdx.Kind = RegKind;
659 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
660 AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc);
662 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
668 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
670 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index)
    [all...]
  /external/llvm/lib/Target/AMDGPU/
SILowerControlFlow.cpp 414 int RegIdx = TRI->getHWRegIndex(SubReg) + Offset;
416 if (RegIdx < 0) {
417 Offset = RegIdx;
418 RegIdx = 0;
423 Reg = RC->getRegister(RegIdx);
  /external/llvm/include/llvm/CodeGen/
LiveVariables.h 274 VarInfo &getVarInfo(unsigned RegIdx);
  /external/llvm/lib/Target/AMDGPU/InstPrinter/
AMDGPUInstPrinter.cpp 213 unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1);
215 O << Type << RegIdx;
219 O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
  /external/llvm/lib/Target/Mips/
MipsSEISelDAGToDAG.h 33 unsigned getMSACtrlReg(const SDValue RegIdx) const;
MipsSEISelDAGToDAG.cpp 71 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
72 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
806 SDValue RegIdx = Node->getOperand(2);
808 getMSACtrlReg(RegIdx), MVT::i32);
838 SDValue RegIdx = Node->getOperand(2);
841 getMSACtrlReg(RegIdx), Value);
    [all...]
  /external/llvm/lib/Target/X86/
X86FastISel.cpp     [all...]
  /external/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp     [all...]

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