| /external/llvm/lib/Target/AMDGPU/ |
| SIFrameLowering.cpp | 180 unsigned Lo = TRI->getSubReg(PreloadedPrivateBufferReg, AMDGPU::sub0_sub1);
186 .addReg(Lo, RegState::Kill);
|
| AMDGPUISelDAGToDAG.cpp | 444 SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
451 SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
[all...] |
| R600ISelLowering.cpp | [all...] |
| SIISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 45 // No relation with Mips Lo register
46 Lo,
301 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
313 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
315 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
334 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
352 // (add %hi(sym), %lo(sym))
357 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
360 DAG.getNode(MipsISD::Lo, DL, Ty, Lo))
[all...] |
| Mips16ISelDAGToDAG.cpp | 49 SDNode *Lo = nullptr, *Hi = nullptr;
56 Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
57 InFlag = SDValue(Lo, 1);
63 return std::make_pair(Lo, Hi);
212 // addiu $2, $2, %lo($CPI1_0)
216 // lwc1 $f0, %lo($CPI1_0)($2)
217 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
|
| MipsSEFrameLowering.cpp | 183 // copy lo, $vr0
193 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
199 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
792 // ISRs require HI/LO to be spilled into kernel registers to be then
[all...] |
| MipsFastISel.cpp | 315 unsigned Lo = Imm & 0xFFFF;
317 if (Lo) {
318 // Both Lo and Hi have nonzero bits.
321 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
[all...] |
| MipsSEISelLowering.cpp | 388 // multHi/Lo: product of multiplication
389 // Lo0: initial value of Lo register
460 // multHi/Lo: product of multiplication
461 // Lo0: initial value of Lo register
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 137 SDValue Lo, Hi;
142 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
147 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
152 std::swap(Lo, Hi);
154 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
164 Lo = Val;
166 std::swap(Lo, Hi);
171 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
173 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
[all...] |
| LegalizeDAG.cpp | 415 SDValue Lo = Val;
421 DAG.getDataLayout().isLittleEndian() ? Lo : Hi,
430 Chain, dl, DAG.getDataLayout().isLittleEndian() ? Hi : Lo, Ptr,
552 SDValue Lo, Hi;
554 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
572 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
584 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
586 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
707 SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32);
710 std::swap(Lo, Hi)
[all...] |
| LegalizeTypesGeneric.cpp | 14 // computation in two identical registers of a smaller type. The Lo/Hi part
32 // These routines assume that the Lo/Hi part is stored first in memory on
33 // little/big-endian machines, followed by the Hi/Lo part. This means that
34 // they cannot be used as is on vectors, for which Lo is always stored first.
36 SDValue &Lo, SDValue &Hi) {
38 GetExpandedOp(Op, Lo, Hi);
41 void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
62 SplitInteger(SoftenedOp, Lo, Hi);
63 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
[all...] |
| LegalizeVectorOps.cpp | 572 SDValue Lo, Hi, ShAmt;
577 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
578 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
595 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
600 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
603 Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT)
[all...] |
| LegalizeFloatTypes.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 281 SDValue Lo, Hi;
282 GetSplitVector(N->getOperand(0), Lo, Hi);
283 Lo = BitConvertToInteger(Lo);
287 std::swap(Lo, Hi);
292 JoinIntegers(Lo, Hi));
[all...] |
| LegalizeVectorTypes.cpp | 576 SDValue Lo, Hi;
592 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
594 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
595 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
596 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
597 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
598 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
599 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
600 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
601 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break
[all...] |
| /external/opencv3/3rdparty/jinja2/ |
| _stringdefs.py | [all...] |
| /external/llvm/include/llvm/Support/ |
| GCOV.h | 198 uint32_t Lo, Hi;
199 if (!readInt(Lo) || !readInt(Hi))
201 Val = ((uint64_t)Hi << 32) | Lo;
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitDouble.cpp | 300 static inline int32_t profitImm(unsigned Lo, unsigned Hi) {
303 if (Lo == 0 || Lo == 0xFFFFFFFF)
307 if (!LoZ1 && !HiZ1 && Lo == Hi)
337 unsigned Lo = D & 0xFFFFFFFFULL;
339 return profitImm(Lo, Hi);
792 // LoR = shl R.lo, #s
793 // TmpR = extractu R.lo, #s, #32-s
797 // TmpR = shr R.lo, #s
801 // LoR = shl R.lo, #
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | [all...] |
| PPCISelDAGToDAG.cpp | 624 unsigned Lo = Imm & 0xFFFF;
628 // Just the Lo bits.
630 } else if (Lo) {
631 // Handle the Hi bits and Lo bits.
712 unsigned Lo = Imm & 0xFFFF;
721 // Just the Lo bits.
722 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
723 } else if (Lo) {
727 // And Lo bits.
729 SDValue(Result, 0), getI32Imm(Lo));
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 580 SDValue Lo(Hi.getNode(), 1);
581 SDValue Ops[] = { Lo, Hi };
597 SDValue Lo(Hi.getNode(), 1);
598 SDValue Ops[] = { Lo, Hi };
694 SDValue Lo(Hi.getNode(), 1);
695 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
702 SDValue Lo(Hi.getNode(), 1);
703 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
713 SDValue Lo(Hi.getNode(), 1);
718 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi)
[all...] |
| /external/valgrind/VEX/priv/ |
| host_mips_isel.c | 367 /* store hi,lo as Ity_I32's */
1689 HReg hi, lo; local
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/clang/lib/Sema/ |
| SemaStmt.cpp | 821 Expr *Lo = CS->getLHS();
823 if (Lo->isTypeDependent() || Lo->isValueDependent()) {
834 CheckConvertedConstantExpression(Lo, CondType, LoVal, CCEK_CaseValue);
839 Lo = ConvLo.get();
843 LoVal = Lo->EvaluateKnownConstInt(Context);
847 Lo = DefaultLvalueConversion(Lo).get();
848 Lo = ImpCastExprToType(Lo, CondType, CK_IntegralCast).get()
[all...] |
