Lines Matching refs:addReg
34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg()))
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg()))
61 .addReg(MI->getOperand(0).getReg())
62 .addReg(MI->getOperand(1).getReg())
63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()))
87 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
88 .addReg(MI->getOperand(1).getReg())
90 .addReg(MI->getOperand(3).getReg());
97 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
98 .addReg(MI->getOperand(1).getReg())
100 .addReg(MI->getOperand(3).getReg())
109 LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R14D);
114 .addReg(SystemZ::R14D)
120 .addReg(SystemZ::R14D)
121 .addReg(MI->getOperand(0).getReg());
130 LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R1D);
135 .addReg(SystemZ::R14D)
142 .addReg(SystemZ::R14D)
149 .addReg(MI->getOperand(0).getReg())
155 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
161 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
177 .addReg(MI->getOperand(0).getReg())
178 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(1).getReg()))
179 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()));
185 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
186 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg()));
207 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(0).getReg()))
208 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg()))
209 .addReg(0).addImm(0);
214 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
215 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
216 .addReg(MI->getOperand(1).getReg())
217 .addReg(0).addImm(0);
257 .addImm(14).addReg(SystemZ::R0D);
260 .addImm(15).addReg(SystemZ::R0D);
