README.txt
1 //===---------------------------------------------------------------------===// 2 // Random notes about and ideas for the SystemZ backend. 3 //===---------------------------------------------------------------------===// 4 5 The initial backend is deliberately restricted to z10. We should add support 6 for later architectures at some point. 7 8 -- 9 10 SystemZDAGToDAGISel::SelectInlineAsmMemoryOperand() is passed "m" for all 11 inline asm memory constraints; it doesn't get to see the original constraint. 12 This means that it must conservatively treat all inline asm constraints 13 as the most restricted type, "R". 14 15 -- 16 17 If an inline asm ties an i32 "r" result to an i64 input, the input 18 will be treated as an i32, leaving the upper bits uninitialised. 19 For example: 20 21 define void @f4(i32 *%dst) { 22 %val = call i32 asm "blah $0", "=r,0" (i64 103) 23 store i32 %val, i32 *%dst 24 ret void 25 } 26 27 from CodeGen/SystemZ/asm-09.ll will use LHI rather than LGHI. 28 to load 103. This seems to be a general target-independent problem. 29 30 -- 31 32 The tuning of the choice between LOAD ADDRESS (LA) and addition in 33 SystemZISelDAGToDAG.cpp is suspect. It should be tweaked based on 34 performance measurements. 35 36 -- 37 38 There is no scheduling support. 39 40 -- 41 42 We don't use the BRANCH ON INDEX instructions. 43 44 -- 45 46 We might want to use BRANCH ON CONDITION for conditional indirect calls 47 and conditional returns. 48 49 -- 50 51 We don't use the TEST DATA CLASS instructions. 52 53 -- 54 55 We only use MVC, XC and CLC for constant-length block operations. 56 We could extend them to variable-length operations too, 57 using EXECUTE RELATIVE LONG. 58 59 MVCIN, MVCLE and CLCLE may be worthwhile too. 60 61 -- 62 63 We don't use CUSE or the TRANSLATE family of instructions for string 64 operations. The TRANSLATE ones are probably more difficult to exploit. 65 66 -- 67 68 We don't take full advantage of builtins like fabsl because the calling 69 conventions require f128s to be returned by invisible reference. 70 71 -- 72 73 ADD LOGICAL WITH SIGNED IMMEDIATE could be useful when we need to 74 produce a carry. SUBTRACT LOGICAL IMMEDIATE could be useful when we 75 need to produce a borrow. (Note that there are no memory forms of 76 ADD LOGICAL WITH CARRY and SUBTRACT LOGICAL WITH BORROW, so the high 77 part of 128-bit memory operations would probably need to be done 78 via a register.) 79 80 -- 81 82 We don't use the halfword forms of LOAD REVERSED and STORE REVERSED 83 (LRVH and STRVH). 84 85 -- 86 87 We don't use ICM or STCM. 88 89 -- 90 91 DAGCombiner doesn't yet fold truncations of extended loads. Functions like: 92 93 unsigned long f (unsigned long x, unsigned short *y) 94 { 95 return (x << 32) | *y; 96 } 97 98 therefore end up as: 99 100 sllg %r2, %r2, 32 101 llgh %r0, 0(%r3) 102 lr %r2, %r0 103 br %r14 104 105 but truncating the load would give: 106 107 sllg %r2, %r2, 32 108 lh %r2, 0(%r3) 109 br %r14 110 111 -- 112 113 Functions like: 114 115 define i64 @f1(i64 %a) { 116 %and = and i64 %a, 1 117 ret i64 %and 118 } 119 120 ought to be implemented as: 121 122 lhi %r0, 1 123 ngr %r2, %r0 124 br %r14 125 126 but two-address optimisations reverse the order of the AND and force: 127 128 lhi %r0, 1 129 ngr %r0, %r2 130 lgr %r2, %r0 131 br %r14 132 133 CodeGen/SystemZ/and-04.ll has several examples of this. 134 135 -- 136 137 Out-of-range displacements are usually handled by loading the full 138 address into a register. In many cases it would be better to create 139 an anchor point instead. E.g. for: 140 141 define void @f4a(i128 *%aptr, i64 %base) { 142 %addr = add i64 %base, 524288 143 %bptr = inttoptr i64 %addr to i128 * 144 %a = load volatile i128 *%aptr 145 %b = load i128 *%bptr 146 %add = add i128 %a, %b 147 store i128 %add, i128 *%aptr 148 ret void 149 } 150 151 (from CodeGen/SystemZ/int-add-08.ll) we load %base+524288 and %base+524296 152 into separate registers, rather than using %base+524288 as a base for both. 153 154 -- 155 156 Dynamic stack allocations round the size to 8 bytes and then allocate 157 that rounded amount. It would be simpler to subtract the unrounded 158 size from the copy of the stack pointer and then align the result. 159 See CodeGen/SystemZ/alloca-01.ll for an example. 160 161 -- 162 163 If needed, we can support 16-byte atomics using LPQ, STPQ and CSDG. 164 165 -- 166 167 We might want to model all access registers and use them to spill 168 32-bit values. 169
