Lines Matching defs:Bit
32 // (((X ^ XORValue) + AddValue) >> Bit)
34 IPMConversion(unsigned xorValue, int64_t addValue, unsigned bit)
35 : XORValue(xorValue), AddValue(addValue), Bit(bit) {}
39 unsigned Bit;
64 // Classify VT as either 32 or 64 bit.
203 // Type legalization will convert 8- and 16-bit atomic operations into
220 // Handle unsigned 32-bit types as signed 64-bit types.
226 // We have native support for a 64-bit CTLZ, via FLOGR.
230 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
422 // We have 64-bit FPR<->GPR moves, but need special handling for
423 // 32-bit forms.
519 // Require a 20-bit signed offset.
558 case 'Q': // Memory with base and unsigned 12-bit displacement
560 case 'S': // Memory with base and signed 20-bit displacement
565 case 'I': // Unsigned 8-bit constant
566 case 'J': // Unsigned 12-bit constant
567 case 'K': // Signed 16-bit constant
568 case 'L': // Signed 20-bit displacement (on all targets we support)
608 case 'I': // Unsigned 8-bit constant
614 case 'J': // Unsigned 12-bit constant
620 case 'K': // Signed 16-bit constant
626 case 'L': // Signed 20-bit displacement (on all targets we support)
727 case 'I': // Unsigned 8-bit constant
734 case 'J': // Unsigned 12-bit constant
741 case 'K': // Signed 16-bit constant
748 case 'L': // Signed 20-bit displacement (on all targets we support)
781 // We do not yet support 128-bit single-element vector types. If the user
1476 // Deal with cases where the result can be taken directly from a bit
1483 // Deal with cases where we can add a value to force the sign bit
1484 // to contain the right value. Putting the bit in 31 means we can
1506 // Next try inverting the value and testing a bit. 0/1 could be
1511 // Handle cases where adding a value forces a non-sign bit to contain
1519 // can be done by inverting the low CC bit and applying one of the
1569 // We must have an 8- or 16-bit load.
1593 // Test whether the high bit of the byte is set.
1596 // Test whether the high bit of the byte is clear.
1682 // The unsigned memory-immediate instructions can handle 16-bit
1687 // The signed memory-immediate instructions can handle 16-bit
1842 // bit is dropped.
1885 // Check for ordered comparisons with the top bit.
1937 // There is no instruction to compare with a 64-bit immediate
2012 // bit 3 for CC==0, bit 0 for CC==3, always false for CC>3.
2018 // bits above bit 3 for CC==0 (always false), bits above bit 0 for CC==3,
2025 // bit 3 and above for CC==0, bit 0 and above for CC==3 (always true),
2119 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
2169 DAG.getConstant(Conversion.Bit, DL, MVT::i32));
2170 if (Conversion.Bit != 31)
2397 // Sign-extend from the low bit.
2517 // Merge them into a single 64-bit address.
2803 // Just do a normal 64-bit multiplication and extract the results.
2808 // Do a full 128-bit multiplication based on UMUL_LOHI64:
2845 // Just do a normal 64-bit multiplication and extract the results.
2866 // We use DSGF for 32-bit division.
2876 // DSG(F) takes a 64-bit dividend, so the even register in the GR128
2904 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
3055 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
3062 // 32-bit operations need no code outside the main loop.
3128 // Op is an ATOMIC_LOAD_SUB operation. Lower 8- and 16-bit operations
3129 // into ATOMIC_LOADW_SUBs and decide whether to convert 32- and 64-bit
3166 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation. Lower the first two
3172 // We have native support for 32-bit compare and swap.
3858 // Try to load a vector constant in which BitsPerElement-bit value Value
3867 // Signed 16-bit values can be replicated using VREPI.
3881 // isRxSBGMask returns the bit numbers for a full 64-bit value,
3883 // bit numbers for an BitsPerElement value, so that 0 denotes
3986 // Use a 64-bit merge high to combine two doubles.
4092 // First try assuming that any undefined bits above the highest set bit
4093 // and below the lowest set bit are 1s. This increases the likelihood of
4582 // Make sure that the least-significant bit of the extracted value
4583 // is the least significant bit of an input.
5007 // Subword operations use 32-bit registers.
5057 // Perform the operation normally and then invert every bit of the field.
5126 // Subword operations use 32-bit registers.
