Lines Matching refs:Emit
383 void ConstPool::Emit(bool require_jump) {
393 // Emit the constant pool. It is preceded by an optional branch if
411 // Emit branch if required
417 // Emit the header.
423 // Emit constant pool entries.
463 assm_->Emit(LDR_x_lit |
533 // Emit unique entries.
591 // Emit constant pool if necessary.
898 // * no_const_pool_before_ < next_constant_pool_check_ and the next emit
956 Emit(BLR | Rn(xzr));
976 Emit(BR | Rn(xn));
985 Emit(BLR | Rn(xn));
991 Emit(RET | Rn(xn));
996 Emit(B | ImmUncondBranch(imm26));
1006 Emit(B_cond | ImmCondBranch(imm19) | cond);
1016 Emit(BL | ImmUncondBranch(imm26));
1027 Emit(SF(rt) | CBZ | ImmCmpBranch(imm19) | Rt(rt));
1039 Emit(SF(rt) | CBNZ | ImmCmpBranch(imm19) | Rt(rt));
1053 Emit(TBZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt));
1068 Emit(TBNZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt));
1081 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd));
1251 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd));
1260 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd));
1269 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd));
1278 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd));
1287 Emit(SF(rd) | BFM | N |
1298 Emit(SF(rd) | SBFM | N |
1309 Emit(SF(rd) | UBFM | N |
1321 Emit(SF(rd) | EXTR | N | Rm(rm) |
1397 Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(rd));
1422 Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd));
1524 Emit(SF(rd) | SDIV | Rm(rm) | Rn(rn) | Rd(rd));
1533 Emit(SF(rd) | UDIV | Rm(rm) | Rn(rn) | Rd(rd));
1624 Emit(addrmodeop | memop);
1679 Emit(LoadLiteralOpFor(rt) | ImmLLiteral(imm19) | Rt(rt));
1697 Emit(op | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
1703 Emit(op | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
1709 Emit(op | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
1717 Emit(op | Rs(rs) | Rt2(x31) | Rn(rn) | Rt(rt));
1723 Emit(LDAR_b | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
1729 Emit(LDAXR_b | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
1735 Emit(STLR_b | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
1743 Emit(STLXR_b | Rs(rs) | Rt2(x31) | Rn(rn) | Rt(rt));
1749 Emit(LDAR_h | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
1755 Emit(LDAXR_h | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
1761 Emit(STLR_h | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
1769 Emit(STLXR_h | Rs(rs) | Rt2(x31) | Rn(rn) | Rt(rt));
1791 Emit(MRS | ImmSystemRegister(sysreg) | Rt(rt));
1797 Emit(MSR | Rt(rt) | ImmSystemRegister(sysreg));
1802 Emit(HINT | ImmHint(code) | Rt(xzr));
1807 Emit(DMB | ImmBarrierDomain(domain) | ImmBarrierType(type));
1812 Emit(DSB | ImmBarrierDomain(domain) | ImmBarrierType(type));
1817 Emit(ISB | ImmBarrierDomain(FullSystem) | ImmBarrierType(BarrierAll));
1824 Emit(FMOV_d_imm | Rd(fd) | ImmFP64(imm));
1831 Emit(FMOV_s_imm | Rd(fd) | ImmFP32(imm));
1838 Emit(op | Rd(rd) | Rn(fn));
1845 Emit(op | Rd(fd) | Rn(rn));
1851 Emit(FPType(fd) | FMOV | Rd(fd) | Rn(fn));
2001 Emit(FPType(fn) | FCMP | Rm(fm) | Rn(fn));
2012 Emit(FPType(fn) | FCMP_zero | Rn(fn));
2021 Emit(FPType(fn) | FCCMP | Rm(fm) | Cond(cond) | Rn(fn) | Nzcv(nzcv));
2031 Emit(FPType(fd) | FCSEL | Rm(fm) | Cond(cond) | Rn(fn) | Rd(fd));
2038 Emit(SF(rd) | FPType(fn) | op | Rn(fn) | Rd(rd));
2100 Emit(SF(rn) | FPType(fd) | SCVTF | Rn(rn) | Rd(fd));
2102 Emit(SF(rn) | FPType(fd) | SCVTF_fixed | FPScale(64 - fbits) | Rn(rn) |
2112 Emit(SF(rn) | FPType(fd) | UCVTF | Rn(rn) | Rd(fd));
2114 Emit(SF(rn) | FPType(fd) | UCVTF_fixed | FPScale(64 - fbits) | Rn(rn) |
2240 Emit(SF(rd) | MoveWideImmediateFixed | mov_op | Rd(rd) |
2256 Emit(SF(rd) | AddSubImmediateFixed | op | Flags(S) |
2268 // extended register mode, and emit an add/sub extended instruction.
2292 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) | Rn(rn) | Rd(rd));
2298 Emit(HLT | ImmException(code));
2304 Emit(BRK | ImmException(code));
2325 // make sure we don't try to emit pools.
2398 Emit(SF(rd) | LogicalImmediateFixed | op | BitN(n, reg_size) |
2420 Emit(SF(rn) | ccmpop | Cond(cond) | Rn(rn) | Nzcv(nzcv));
2428 Emit(SF(rn) | op | Rn(rn) | Rd(rd));
2435 Emit(FPType(fn) | op | Rn(fn) | Rd(fd));
2445 Emit(FPType(fd) | op | Rm(fm) | Rn(fn) | Rd(fd));
2455 Emit(FPType(fd) | op | Rm(fm) | Rn(fn) | Rd(fd) | Ra(fa));
2527 Emit(SF(rd) | op | Flags(S) |
2540 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) |
2561 Emit(LoadStoreUnsignedOffsetFixed | memop |
2566 Emit(LoadStoreUnscaledOffsetFixed | memop | ImmLS(offset));
2585 Emit(LoadStoreRegisterOffsetFixed | memop | Rm(addr.regoffset()) |
2593 Emit(LoadStorePreIndexFixed | memop | ImmLS(offset));
2596 Emit(LoadStorePostIndexFixed | memop | ImmLS(offset));
3020 // We emit a constant pool when:
3034 // Emit veneers for branches that would go out of range during emission of the
3049 constpool_.Emit(require_jump);
3107 // Patch the branch to point to the current position, and emit a branch
