Home | History | Annotate | Download | only in arm64

Lines Matching refs:Lsr

2213     __ Lsr(result_reg, result_reg, 32);
2520 __ Add(result, dividend, Operand(dividend, LSR, 31));
2523 __ Add(result, dividend, Operand(result, LSR, 32 - shift));
4584 __ Lsr(result, left, right);
4606 case Token::SHR: __ Lsr(result, left, shift_count); break;
4646 __ Lsr(result, left, result);
4679 __ Lsr(result, left, shift_count);