| /external/llvm/lib/Target/AArch64/ |
| AArch64StorePairSuppress.cpp | 143 unsigned BaseReg;
145 if (TII->getMemOpBaseRegImmOfs(&MI, BaseReg, Offset, TRI)) {
146 if (PrevBaseReg == BaseReg) {
155 PrevBaseReg = BaseReg;
|
| AArch64LoadStoreOptimizer.cpp | 121 unsigned BaseReg, int Offset);
880 unsigned BaseReg = getLdStBaseOp(FirstMI).getReg();
890 if (FirstMI->modifiesRegister(BaseReg, TRI))
946 if (BaseReg == MIBaseReg && ((Offset == MIOffset + OffsetStride) ||
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 248 unsigned BaseReg = MI->getOperand(0).getReg();
250 if (MI->getOperand(i).getReg() == BaseReg)
258 printRegName(O, BaseReg);
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 189 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg);
204 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
211 if (IndexReg.getReg() || BaseReg.getReg()) {
213 if (BaseReg.getReg())
|
| X86IntelInstPrinter.cpp | 159 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
174 if (BaseReg.getReg()) {
193 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| /external/llvm/lib/CodeGen/ |
| ImplicitNullChecks.cpp | 327 unsigned BaseReg, Offset;
328 if (TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI))
329 if (MI->mayLoad() && !MI->isPredicable() && BaseReg == PointerReg &&
|
| LocalStackSlotAllocation.cpp | 255 lookupCandidateBaseReg(unsigned BaseReg,
264 return TRI->isFrameOffsetLegal(MI, BaseReg, Offset);
330 unsigned BaseReg = 0;
366 if (UsedBaseReg && lookupCandidateBaseReg(BaseReg, BaseOffset,
369 DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n");
387 BaseReg, BaseOffset, FrameSizeAdjust,
396 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
398 DEBUG(dbgs() << " Materializing base register " << BaseReg <<
404 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx,
415 assert(BaseReg != 0 && "Unable to allocate virtual base register!")
[all...] |
| MachineScheduler.cpp | [all...] |
| CodeGenPrepare.cpp | [all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsNaClELFStreamer.cpp | 122 unsigned BaseReg = MI.getOperand(AddrIdx).getReg();
123 emitMask(BaseReg, LoadStoreStackMaskReg, STI);
|
| /external/llvm/lib/Target/X86/ |
| X86SelectionDAGInfo.cpp | 40 unsigned BaseReg = TRI->getBaseRegister();
42 if (BaseReg == R)
|
| X86AsmPrinter.cpp | 245 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
250 bool HasBaseReg = BaseReg.getReg() != 0;
252 BaseReg.getReg() == X86::RIP)
310 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
325 if (BaseReg.getReg()) {
343 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| X86MCInstLower.cpp | [all...] |
| X86InstrInfo.cpp | [all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| Store.cpp | 274 const MemRegion *BaseReg =
278 return loc::MemRegionVal(BaseReg);
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 128 // ARM::t2STMIA (with no basereg writeback) has no Thumb1 equivalent.
421 unsigned BaseReg = MI->getOperand(0).getReg();
422 assert(isARMLowRegister(BaseReg));
428 if (MI->getOperand(i).getReg() == BaseReg) {
450 unsigned BaseReg = MI->getOperand(1).getReg();
451 if (BaseReg != ARM::SP)
463 unsigned BaseReg = MI->getOperand(1).getReg();
464 if (BaseReg == ARM::SP &&
469 } else if (!isARMLowRegister(BaseReg) ||
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMBaseInstrInfo.cpp | 165 unsigned BaseReg = Base.getReg();
181 .addReg(BaseReg).addImm(Amt)
188 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
193 .addReg(BaseReg).addReg(OffReg)
204 .addReg(BaseReg).addImm(Amt)
209 .addReg(BaseReg).addReg(OffReg)
231 .addReg(BaseReg).addImm(0).addImm(Pred);
235 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonStoreWidening.cpp | 243 unsigned BaseReg = getBaseAddressRegister(BaseStore);
264 if (BR == BaseReg) {
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86Operand.h | 55 unsigned BaseReg;
117 return Mem.BaseReg;
502 Res->Mem.BaseReg = 0;
516 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
521 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
529 Res->Mem.BaseReg = BaseReg;
|
| X86AsmParser.cpp | 266 unsigned BaseReg, IndexReg, TmpReg, Scale;
276 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
280 unsigned getBaseReg() { return BaseReg; }
384 // If we already have a BaseReg, then assume this is the IndexReg with
386 if (!BaseReg) {
387 BaseReg = TmpReg;
389 assert (!IndexReg && "BaseReg/IndexReg already set!");
421 // If we already have a BaseReg, then assume this is the IndexReg with
423 if (!BaseReg) {
424 BaseReg = TmpReg
1012 unsigned basereg = local
1021 unsigned basereg = local
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
64 if (is16BitMode(STI) && BaseReg.getReg() == 0 &&
67 if ((BaseReg.getReg() != 0 &&
68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
226 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
229 if ((BaseReg.getReg() != 0 &&
230 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
241 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
244 if ((BaseReg.getReg() != 0 &&
245 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) |
[all...] |
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 680 unsigned BaseReg = 0;
682 if (ParseRegister(BaseReg, S, E)) {
692 Operands.push_back(SparcOperand::CreateMEMr(BaseReg, S, E));
708 Offset->isImm() ? SparcOperand::MorphToMEMri(BaseReg, std::move(Offset))
709 : SparcOperand::MorphToMEMrr(BaseReg, std::move(Offset)));
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 460 for (const SCEV *BaseReg : BaseRegs)
461 if (RegUses.isRegUsedByUsesOtherThan(BaseReg, LUIdx))
476 for (const SCEV *BaseReg : BaseRegs) {
478 OS << "reg(" << *BaseReg << ')';
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 194 bool expandLoadAddress(unsigned DstReg, unsigned BaseReg,
[all...] |
