/external/clang/lib/StaticAnalyzer/Core/ |
CheckerHelpers.cpp | 35 const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(S); 37 if (DR && isa<EnumConstantDecl>(DR->getDecl())) 49 const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(S); 51 if (DR) 52 if (const VarDecl *VD = dyn_cast<VarDecl>(DR->getDecl()))
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/device/google/contexthub/firmware/src/platform/stm32f4xx/ |
crc.c | 25 volatile uint32_t DR; 61 if (mCrcRegs->DR == crc) 66 mCrcRegs->DR = revCrc32Word(crc, mCrcRegs->DR, 8); 69 mCrcRegs->DR = words[i]; 77 mCrcRegs->DR = word; 80 crc = mCrcRegs->DR;
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usart.c | 26 volatile uint16_t DR; 155 block->DR = (uint8_t)c;
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rtc.c | 35 volatile uint32_t DR; /* 0x04 */ 142 RTC->DR = 0b1100000100000001; 148 * 4 RTC cycles after set - must poll RSF before read DR or TR */ 253 uint32_t dr, tr, ssr; local 262 // decrements (which can propagate changes to tr and dr) 266 dr = RTC->DR; 269 month = (((dr >> 12) & 0x1) * 10) + ((dr >> 8) & 0xf) - 1; 270 time_s = (((((dr >> 4) & 0x3) * 10) + (dr & 0xF) - 1) + (month << 5) - adjust[month]) * 86400ULL [all...] |
spi.c | 72 volatile uint32_t DR; 158 mode.periphAddr = (uintptr_t)®s->DR; 383 (void)regs->DR; 386 regs->DR = mode->txWord; 504 * controller will just keep reading the existing value from DR anytime it 507 regs->DR = pdev->state.txWord;
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bl.c | 39 volatile uint32_t DR; 96 volatile uint32_t DR; 837 (void)spi->DR; 839 (void)spi->DR; 845 spi->DR = val; 847 return spi->DR; 918 if (spi->DR == BL_SYNC_IN) [all...] |
/external/clang/lib/Analysis/ |
PseudoConstantAnalysis.cpp | 70 if (const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(E)) 71 return DR->getDecl(); 201 const DeclRefExpr *DR = cast<DeclRefExpr>(Head); 202 if (const VarDecl *VD = dyn_cast<VarDecl>(DR->getDecl())) {
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BodyFarm.cpp | 110 DeclRefExpr *DR = 119 return DR; 205 DeclRefExpr *DR = M.makeDeclRefExpr(Block); 206 ImplicitCastExpr *ICE = M.makeLvalueToRvalue(DR, Ty); 266 DeclRefExpr *DR = M.makeDeclRefExpr(PV); 267 ImplicitCastExpr *ICE = M.makeLvalueToRvalue(DR, Ty);
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LiveVariables.cpp | 208 void VisitDeclRefExpr(DeclRefExpr *DR); 340 if (DeclRefExpr *DR = dyn_cast<DeclRefExpr>(LHS)) 341 if (const VarDecl *VD = dyn_cast<VarDecl>(DR->getDecl())) { 352 observer->observerKill(DR); 366 void TransferFunctions::VisitDeclRefExpr(DeclRefExpr *DR) { 367 if (const VarDecl *D = dyn_cast<VarDecl>(DR->getDecl())) 368 if (!isAlwaysAlive(D) && LV.inAssignment.find(DR) == LV.inAssignment.end()) 382 DeclRefExpr *DR = nullptr; 389 else if ((DR = dyn_cast<DeclRefExpr>(cast<Expr>(element)->IgnoreParens()))) { 390 VD = cast<VarDecl>(DR->getDecl()) [all...] |
ReachableCode.cpp | 35 const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(Ex); 36 if (!DR) 38 return isa<EnumConstantDecl>(DR->getDecl());
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/external/clang/www/ |
make_cxx_dr_status | 16 class DR: 23 def parse(dr): 26 for col in dr.split('</TR>', 1)[0].split('<TD')[1:] 32 return DR(section, issue, url, status, title) 47 drs = sorted((parse(dr) for dr in file(index, 'r').read().split('<TR>')[2:]), 48 key = lambda dr: dr.issue) 136 assert False, 'unknown status %s for issue %s' % (status, dr.issue) 140 for dr in drs [all...] |
/external/harfbuzz_ng/src/ |
hb-ot-shape-complex-arabic-table.hh | 24 #define DR JOINING_GROUP_DALATH_RISH 47 /* 0700 */ X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,A,X,D,D,D,DR,DR,R,R,R,D,D,D,D,R,D, 48 /* 0720 */ D,D,D,D,D,D,D,D,R,D,DR,D,R,D,D,DR,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X, 165 #undef DR
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/external/clang/lib/StaticAnalyzer/Checkers/ |
DereferenceChecker.cpp | 65 const DeclRefExpr *DR = cast<DeclRefExpr>(Ex); 66 if (const VarDecl *VD = dyn_cast<VarDecl>(DR->getDecl())) { 69 Ranges.push_back(DR->getSourceRange());
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DeadStoresChecker.cpp | 54 bool VisitDeclRefExpr(DeclRefExpr *DR) { 56 if (const VarDecl *D = dyn_cast<VarDecl>(DR->getDecl())) 229 void CheckDeclRef(const DeclRefExpr *DR, const Expr *Val, DeadStoreKind dsk, 231 if (const VarDecl *VD = dyn_cast<VarDecl>(DR->getDecl())) 232 CheckVarDecl(VD, DR, Val, dsk, Live); 245 const DeclRefExpr *DR; 247 if ((DR = dyn_cast<DeclRefExpr>(BRHS->getLHS()->IgnoreParenCasts()))) 248 if (DR->getDecl() == VD) 251 if ((DR = dyn_cast<DeclRefExpr>(BRHS->getRHS()->IgnoreParenCasts()))) 252 if (DR->getDecl() == VD [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonBitSimplify.cpp | 935 unsigned DR = UseI->getOperand(0).getReg(); 936 if (DR == R) [all...] |
HexagonGenMux.cpp | 72 MuxInfo(MachineBasicBlock::iterator It, unsigned DR, unsigned PR, 75 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(D1), 205 unsigned DR = MI->getOperand(0).getReg(); 206 if (isRegPair(DR)) 211 CondsetMap::iterator F = CM.find(DR); 221 auto It = CM.insert(std::make_pair(DR, CondsetInfo())); 233 // There is now a complete definition of DR, i.e. we have the predicate 268 if (DU.Defs[PR] || DU.Defs[DR] || DU.Uses[DR]) { 285 ML.push_back(MuxInfo(At, DR, PR, SrcT, SrcF, Def1, Def2)) [all...] |
HexagonGenPredicate.cpp | 457 Register DR = I->getOperand(0); 459 if (!TargetRegisterInfo::isVirtualRegister(DR.R)) 463 if (MRI->getRegClass(DR.R) != PredRC) 467 assert(!DR.S && !SR.S && "Unexpected subregister"); 468 MRI->replaceRegWith(DR.R, SR.R);
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HexagonEarlyIfConv.cpp | 804 unsigned DR = PN->getOperand(0).getReg(); 805 const TargetRegisterClass *RC = MRI->getRegClass(DR); [all...] |
HexagonExpandCondsets.cpp | 721 unsigned DR = MD.getReg(), DSR = MD.getSubReg(); 726 if (MachineInstr *TfrT = genTfrFor(MI->getOperand(2), DR, DSR, MP, true)) 728 if (MachineInstr *TfrF = genTfrFor(MI->getOperand(3), DR, DSR, MP, false)) [all...] |
/toolchain/binutils/binutils-2.25/opcodes/ |
msp430-decode.c | 80 #define DR(r) OP (0, MSP430_Operand_Register, r, 0) 187 DR (reg); 375 ID (MSO_mov); SM (srcr, 0); DR (dstr); 399 ID (MSO_mov); SI (srcr); DR (dstr); 423 ID (MSO_mov); SA ((srcr << 16) + IMMU(2)); DR (dstr); 447 ID (MSO_mov); SM (srcr, IMMS(2)); DR (dstr); 475 ID (MSO_rrc); DR (dstr); SR (dstr); 549 ID (MSO_mov); SC ((srcr << 16) + IMMU(2)); DR (dstr); 573 ID (MSO_cmp); SC ((srcr << 16) + IMMU(2)); DR (dstr); 598 ID (MSO_add); SC ((srcr << 16) + IMMU(2)); DR (dstr) [all...] |
rl78-decode.c | 109 #define DR(r) OP (0, RL78_Operand_Register, RL78_Reg_##r, 0) 116 #define DCY() DR(PSW); DB(0) 227 ID(add); W(); DR(AX); SRW(rw); Fzac; 242 ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac; 257 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac; 272 ID(add); W(); DR(AX); SM(None, SADDR); Fzac; 287 ID(xch); DR(A); SR(X); 304 ID(mov); DR(A); SM(B, IMMU(2)); 336 ID(add); DR(A); SM(None, SADDR); Fzac; 351 ID(add); DR(A); SC(IMMU(1)); Fzac [all...] |
rx-decode.c | 108 #define DR(r) OP (0, RX_Operand_Register, r, 0) 415 ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); DR(rdst); F_OSZC; 540 ID(add); SPm(ss, rsrc, mx); DR(rdst); F_OSZC; 601 ID(mul); SPm(ss, rsrc, mx); DR(rdst); F_____; 662 ID(and); SPm(ss, rsrc, mx); DR(rdst); F__SZ_; 723 ID(or); SPm(ss, rsrc, mx); DR(rdst); F__SZ_; 788 ID(sbb); SPm(sp, rsrc, mx); DR(rdst); F_OSZC; 825 ID(max); SPm(ss, rsrc, mx); DR(rdst); 862 ID(min); SPm(ss, rsrc, mx); DR(rdst); 899 ID(emul); SPm(ss, rsrc, mx); DR(rdst) [all...] |
/external/llvm/tools/llvm-readobj/ |
MachODumper.cpp | 442 DataRefImpl DR = Section.getRawDataRefImpl(); 447 ArrayRef<char> RawName = Obj->getSectionRawName(DR); 448 StringRef SegmentName = Obj->getSectionFinalSegmentName(DR); 449 ArrayRef<char> RawSegmentName = Obj->getSectionRawFinalSegmentName(DR); 534 DataRefImpl DR = Reloc.getRawDataRefImpl(); 535 MachO::any_relocation_info RE = Obj->getRelocation(DR); 548 section_iterator SecI = Obj->getRelocationSection(DR);
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/external/clang/lib/Sema/ |
SemaLookup.cpp | 821 DeclContext::lookup_result DR = DC->lookup(R.getLookupName()); 822 for (DeclContext::lookup_iterator I = DR.begin(), E = DR.end(); I != E; [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZISelDAGToDAG.cpp | 53 DispRange DR; 63 SystemZAddressingMode(AddrForm form, DispRange dr) 64 : Form(form), DR(dr), Base(), Disp(0), Index(), 161 // Try to match Addr as a FormBD address with displacement type DR. 164 bool selectBDAddr(SystemZAddressingMode::DispRange DR, SDValue Addr, 167 // Try to match Addr as a FormBDX address with displacement type DR. 170 bool selectMVIAddr(SystemZAddressingMode::DispRange DR, SDValue Addr, 174 // displacement type DR. Return true on success, storing the base, 177 SystemZAddressingMode::DispRange DR, SDValue Addr [all...] |