| /external/llvm/lib/Target/AMDGPU/ |
| SIFrameLowering.cpp | 181 unsigned Hi = TRI->getSubReg(PreloadedPrivateBufferReg, AMDGPU::sub2_sub3);
188 .addReg(Hi, RegState::Kill);
|
| AMDGPUISelDAGToDAG.cpp | 447 SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
452 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
[all...] |
| R600ISelLowering.cpp | [all...] |
| SIISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 41 // No relation with Mips Hi register
42 Hi,
334 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
340 SDValue Hi =
341 DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(N, Ty, DAG, HiFlag));
342 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
343 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
352 // (add %hi(sym), %lo(sym))
356 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI)
[all...] |
| Mips16ISelDAGToDAG.cpp | 49 SDNode *Lo = nullptr, *Hi = nullptr;
61 Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag);
63 return std::make_pair(Lo, Hi);
211 // lui $2, %hi($CPI1_0)
215 // lui $2, %hi($CPI1_0)
|
| MipsSEFrameLowering.cpp | 185 // copy hi, $vr1
194 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
201 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
792 // ISRs require HI/LO to be spilled into kernel registers to be then
[all...] |
| MipsFastISel.cpp | 316 unsigned Hi = (Imm >> 16) & 0xFFFF;
318 // Both Lo and Hi have nonzero bits.
320 emitInst(Mips::LUi, TmpReg).addImm(Hi);
323 emitInst(Mips::LUi, ResultReg).addImm(Hi);
[all...] |
| MipsSEISelLowering.cpp | 390 // Hi0: initial value of Hi register
462 // Hi0: initial value of Hi register
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 137 SDValue Lo, Hi;
144 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
148 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
152 std::swap(Lo, Hi);
154 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
160 Hi = getCopyFromParts(DAG, DL,
166 std::swap(Lo, Hi);
168 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
169 Hi
[all...] |
| LegalizeDAG.cpp | 416 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
421 DAG.getDataLayout().isLittleEndian() ? Lo : Hi,
430 Chain, dl, DAG.getDataLayout().isLittleEndian() ? Hi : Lo, Ptr,
547 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
552 SDValue Lo, Hi;
560 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
566 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
581 DAG.getConstant(NumBits, dl, TLI.getShiftAmountTy(Hi.getValueType(),
583 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
587 Hi.getValue(1))
[all...] |
| LegalizeTypesGeneric.cpp | 14 // computation in two identical registers of a smaller type. The Lo/Hi part
32 // These routines assume that the Lo/Hi part is stored first in memory on
33 // little/big-endian machines, followed by the Hi/Lo part. This means that
36 SDValue &Lo, SDValue &Hi) {
38 GetExpandedOp(Op, Lo, Hi);
41 void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
62 SplitInteger(SoftenedOp, Lo, Hi);
64 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
71 GetExpandedOp(InOp, Lo, Hi);
[all...] |
| LegalizeVectorOps.cpp | 572 SDValue Lo, Hi, ShAmt;
589 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
590 Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
594 if (Hi.getNode())
595 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
[all...] |
| LegalizeFloatTypes.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 281 SDValue Lo, Hi;
282 GetSplitVector(N->getOperand(0), Lo, Hi);
284 Hi = BitConvertToInteger(Hi);
287 std::swap(Lo, Hi);
292 JoinIntegers(Lo, Hi));
783 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
786 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
787 DAG.getConstant(0, DL, Hi.getValueType()),
[all...] |
| LegalizeVectorTypes.cpp | 576 SDValue Lo, Hi;
592 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
594 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
595 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
596 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
597 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
598 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
599 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
600 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
601 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break
[all...] |
| /external/llvm/include/llvm/Support/ |
| GCOV.h | 198 uint32_t Lo, Hi;
199 if (!readInt(Lo) || !readInt(Hi))
201 Val = ((uint64_t)Hi << 32) | Lo;
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitDouble.cpp | 300 static inline int32_t profitImm(unsigned Lo, unsigned Hi) {
305 if (Hi == 0 || Hi == 0xFFFFFFFF)
307 if (!LoZ1 && !HiZ1 && Lo == Hi)
338 unsigned Hi = D >> 32;
339 return profitImm(Lo, Hi);
794 // HiR = or (TmpR, asl(R.hi, #s))
796 // HiR = shr R.hi, #s
798 // LoR = insert TmpR, R.hi, #s, #32-s
824 // HiR = or (TmpR, asl(R.hi, #s)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | [all...] |
| PPCISelDAGToDAG.cpp | 631 // Handle the Hi bits and Lo bits.
634 // Just the Hi bits.
713 unsigned Hi = (Imm >> 16) & 0xFFFF;
724 // Handle the Hi bits.
725 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
726 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
731 // Just the Hi bits.
732 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
747 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
749 SDValue(Result, 0), getI32Imm(Hi));
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 577 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
580 SDValue Lo(Hi.getNode(), 1);
581 SDValue Ops[] = { Lo, Hi };
594 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
597 SDValue Lo(Hi.getNode(), 1);
598 SDValue Ops[] = { Lo, Hi };
691 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
694 SDValue Lo(Hi.getNode(), 1);
695 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
699 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl
[all...] |
| /external/valgrind/VEX/priv/ |
| host_mips_isel.c | 367 /* store hi,lo as Ity_I32's */
1689 HReg hi, lo; local
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/chromium-trace/catapult/tracing/third_party/d3/ |
| d3.min.js | [all...] |
| /external/clang/lib/Sema/ |
| SemaStmt.cpp | [all...] |
