| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrBuilder.h | 31 const MCInstrDesc &MCID = MI->getDesc();
33 if (MCID.mayLoad())
35 if (MCID.mayStore())
|
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 22 const MCInstrDesc &MCID = MI->getDesc();
23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
26 unsigned Opcode = MCID.getOpcode();
43 const MCInstrDesc &MCID = MI->getDesc();
44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
|
| MLxExpansionPass.cpp | 187 const MCInstrDesc &MCID = MI->getDesc();
188 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
191 unsigned Opcode = MCID.getOpcode();
344 const MCInstrDesc &MCID = MI->getDesc();
352 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
362 if (!TII->isFpMLxInstruction(MCID.getOpcode(),
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| Thumb2ITBlockPass.cpp | 155 const MCInstrDesc &MCID = MI->getDesc();
157 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
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| ARMBaseRegisterInfo.cpp | 572 const MCInstrDesc &MCID = TII.get(ADDriOpc);
573 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
575 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
|
| Thumb2SizeReduction.cpp | 220 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) {
221 for (const MCPhysReg *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
567 const MCInstrDesc &MCID = MI->getDesc();
568 if (MCID.hasOptionalDef() &&
569 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
717 const MCInstrDesc &MCID = MI->getDesc();
718 if (MCID.hasOptionalDef()) {
719 unsigned NumOps = MCID.getNumOperands();
745 unsigned NumOps = MCID.getNumOperands();
747 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()
[all...] |
| /external/llvm/lib/CodeGen/ |
| ScoreboardHazardRecognizer.cpp | 129 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
130 if (!MCID) {
134 unsigned idx = MCID->getSchedClass();
185 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
186 assert(MCID && "The scheduler must filter non-machineinstrs");
187 if (DAG->TII->isZeroCost(MCID->Opcode))
194 unsigned idx = MCID->getSchedClass();
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| ExecutionDepsFix.cpp | 511 const MCInstrDesc &MCID = MI->getDesc();
513 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
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| MIRPrinter.cpp | 513 const MCInstrDesc &MCID = MI.getDesc();
517 // Ignore the defined registers as MCID marks only the uses as tied.
519 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
|
| RegAllocFast.cpp | 812 const MCInstrDesc &MCID = MI->getDesc();
[all...] |
| MachineInstr.cpp | 633 if (MCID->ImplicitDefs)
634 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
637 if (MCID->ImplicitUses)
638 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
648 : MCID(&tid), Parent(nullptr), Operands(nullptr), NumOperands(0), Flags(0),
654 if (unsigned NumOps = MCID->getNumOperands() +
655 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
667 : MCID(&MI.getDesc()), Parent(nullptr), Operands(nullptr), NumOperands(0),
735 assert(MCID && "Cannot add operands before providing an instr descriptor")
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 153 const MCInstrDesc &MCID = MI->getDesc();
155 if (MCID.mayLoad())
157 if (MCID.mayStore())
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 324 const MCInstrDesc &MCID = MIB->getDesc();
325 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
326 MCID.OpInfo[IIOpNum].isOptionalDef();
361 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
[all...] |
| ScheduleDAGFast.cpp | 257 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
258 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
259 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
264 if (MCID.isCommutable())
440 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
441 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
442 NumRes = MCID.getNumDefs();
443 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
519 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
520 if (!MCID.ImplicitDefs
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonAsmBackend.cpp | 181 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI);
186 MCID.isBranch()) ||
|
| HexagonMCChecker.cpp | 58 const MCInstrDesc& MCID = HexagonMCInstrInfo::getDesc(MCII, MCI);
63 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
88 if (const MCPhysReg *ImpDef = MCID.getImplicitDefs())
92 if (Hexagon::R31 != R && MCID.isCall())
117 for (unsigned i = 0; i < MCID.getNumDefs(); ++i) {
200 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
214 if (MCID.isBranch())
|
| HexagonMCCodeEmitter.cpp | 257 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
279 if (MCID.isBranch())
284 } else if (MCID.isBranch())
287 switch (MCID.getOpcode()) {
336 if (MCID.mayStore() || MCID.mayLoad()) {
337 for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses;
418 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
426 DEBUG(dbgs() << "Opcode: " << MCID.getOpcode() << "\n");
489 if (MCID.isBranch() || MCID.isCall())
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 101 const MCInstrDesc &MCID = get(Opc);
102 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXReplaceImageHandles.cpp | 81 const MCInstrDesc &MCID = MI.getDesc();
83 if (MCID.TSFlags & NVPTXII::IsTexFlag) {
89 if (!(MCID.TSFlags & NVPTXII::IsTexModeUnifiedFlag)) {
95 } else if (MCID.TSFlags & NVPTXII::IsSuldMask) {
97 1 << (((MCID.TSFlags & NVPTXII::IsSuldMask) >> NVPTXII::IsSuldShift) - 1);
105 } else if (MCID.TSFlags & NVPTXII::IsSustFlag) {
112 } else if (MCID.TSFlags & NVPTXII::IsSurfTexQueryFlag) {
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
32 if (!MCID)
35 if (!MCID->mayLoad())
57 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
58 if (!MCID)
61 if (!MCID->isBranch())
87 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID,
92 unsigned IIC = MCID->getSchedClass();
125 if (NSlots == 1 && PPC::getNonRecordFormOpcode(MCID->getOpcode()) != -1)
149 const MCInstrDesc *MCID = DAG->getInstrDesc(SU)
[all...] |
| PPCRegisterInfo.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 74 const MCInstrDesc *MCID; // Instruction descriptor.
116 MachineInstr(MachineFunction &, const MCInstrDesc &MCID, DebugLoc dl,
267 const MCInstrDesc &getDesc() const { return *MCID; }
270 unsigned getOpcode() const { return MCID->Opcode; }
391 return hasProperty(MCID::Variadic, Type);
397 return hasProperty(MCID::HasOptionalDef, Type);
403 return hasProperty(MCID::Pseudo, Type);
407 return hasProperty(MCID::Return, Type);
411 return hasProperty(MCID::Call, Type);
418 return hasProperty(MCID::Barrier, Type)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.cpp | 327 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
329 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
332 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
|
| AArch64ConditionalCompares.cpp | 593 const MCInstrDesc &MCID = TII->get(Opc);
596 MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF));
598 BuildMI(*Head, Head->end(), TermDL, MCID)
605 TII->getRegClass(MCID, 1, TRI, *MF));
650 const MCInstrDesc &MCID = TII->get(Opc);
652 TII->getRegClass(MCID, 0, TRI, *MF));
655 TII->getRegClass(MCID, 1, TRI, *MF));
657 BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID)
|
| /external/llvm/include/llvm/MC/ |
| MCInstrDesc.h | 92 namespace MCID {
200 bool isVariadic() const { return Flags & (1 << MCID::Variadic); }
204 bool hasOptionalDef() const { return Flags & (1 << MCID::HasOptionalDef); }
208 bool isPseudo() const { return Flags & (1 << MCID::Pseudo); }
211 bool isReturn() const { return Flags & (1 << MCID::Return); }
214 bool isCall() const { return Flags & (1 << MCID::Call); }
219 bool isBarrier() const { return Flags & (1 << MCID::Barrier); }
227 bool isTerminator() const { return Flags & (1 << MCID::Terminator); }
233 bool isBranch() const { return Flags & (1 << MCID::Branch); }
237 bool isIndirectBranch() const { return Flags & (1 << MCID::IndirectBranch);
[all...] |
