| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 123 unsigned NumOps = Outs.size();
124 for (unsigned i = 0; i != NumOps; ++i) {
141 unsigned NumOps = ArgVTs.size();
142 for (unsigned i = 0; i != NumOps; ++i) {
|
| MachineRegisterInfo.cpp | 136 unsigned NumOps = MI->getNumOperands();
137 if (!(MO >= MO0 && MO < MO0+NumOps)) {
231 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
240 unsigned NumOps) {
241 assert(Src != Dst && NumOps && "Noop moveOperands");
245 if (Dst >= Src && Dst < Src + NumOps) {
247 Dst += NumOps - 1;
248 Src += NumOps - 1;
277 } while (--NumOps);
|
| MachineInstr.cpp | 654 if (unsigned NumOps = MCID->getNumOperands() +
656 CapOperands = OperandCapacity::get(NumOps);
719 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
722 unsigned NumOps, MachineRegisterInfo *MRI) {
724 return MRI->moveOperands(Dst, Src, NumOps);
727 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
[all...] |
| MachineVerifier.cpp | 765 unsigned NumOps;
766 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
771 NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
[all...] |
| TwoAddressInstructionPass.cpp | 476 for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {
[all...] |
| /external/llvm/lib/IR/ |
| Instructions.cpp | 133 unsigned NumOps = e + e / 2;
134 if (NumOps < 2) NumOps = 2; // 2 op PHI nodes are VERY common.
136 ReservedSpace = NumOps;
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.cpp | 204 unsigned NumOps = Node->getNumOperands();
205 if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
206 Chain = Node->getOperand(NumOps-1).getNode();
[all...] |
| LegalizeTypes.cpp | 433 for (unsigned i = 0, NumOps = Node.getNumOperands(); i < NumOps; ++i)
[all...] |
| ScheduleDAGFast.cpp | 493 unsigned NumOps = Node->getNumOperands();
494 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
495 --NumOps; // Ignore the glue operand.
497 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
681 unsigned NumOps = N->getNumOperands();
682 if (unsigned NumLeft = NumOps) {
688 if (NumLeft == NumOps && Op.getValueType() == MVT::Glue) {
|
| ScheduleDAGRRList.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 162 unsigned NumOps = N->getNumOperands();
173 SDValue Glue = N->getGluedNode() ? N->getOperand(NumOps-1)
178 for(unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {
223 assert((i+2 < NumOps) && "Invalid number of operands in inline asm");
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86BaseInfo.h | 632 unsigned NumOps = Desc.getNumOperands();
634 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
636 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
641 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
642 Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1)
646 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0)
|
| X86MCCodeEmitter.cpp | 711 unsigned NumOps = Desc.getNumOperands();
861 unsigned RcOperand = NumOps-1;
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86CallFrameOptimization.cpp | 489 unsigned NumOps = DefMov->getDesc().getNumOperands();
490 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
|
| X86FloatingPoint.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenInstruction.cpp | 72 unsigned NumOps = 1;
94 NumOps = NumArgs;
120 NumOps, MIOpInfo);
121 MIOperandNo += NumOps;
|
| DAGISelMatcherEmitter.cpp | 678 unsigned NumOps = P.getNumOperands();
681 ++NumOps; // Get the chained node too.
684 OS << " Result.resize(NextRes+" << NumOps << ");\n";
699 for (unsigned i = 0; i != NumOps; ++i)
|
| AsmWriterEmitter.cpp | 383 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
384 assert(NumOps <= Inst->Operands.size() &&
387 Inst->Operands.begin()+NumOps);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonGenPredicate.cpp | 355 unsigned NumOps = MI->getNumOperands();
356 for (unsigned i = 0; i < NumOps; ++i) {
392 NumOps = 2;
408 for (unsigned i = 1; i < NumOps; ++i) {
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 719 unsigned NumOps = MCID.getNumOperands();
720 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
721 if (HasCC && MI->getOperand(NumOps-1).isDead())
745 unsigned NumOps = MCID.getNumOperands();
747 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
814 unsigned NumOps = MCID.getNumOperands();
815 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
816 if (HasCC && MI->getOperand(NumOps-1).isDead())
840 unsigned NumOps = MCID.getNumOperands();
842 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()
[all...] |
| ARMConstantIslandPass.cpp | 624 unsigned NumOps = MI->getDesc().getNumOperands();
626 MI->getOperand(NumOps - (MI->isPredicable() ? 2 : 1));
[all...] |
| ARMBaseInstrInfo.cpp | 159 unsigned NumOps = MCID.getNumOperands();
163 const MachineOperand &Offset = MI->getOperand(NumOps-3);
167 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
168 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Scalarizer.cpp | 576 unsigned NumOps = PHI.getNumOperands();
578 Res[I] = Builder.CreatePHI(VT->getElementType(), NumOps,
581 for (unsigned I = 0; I < NumOps; ++I) {
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
| SystemZInstrInfo.cpp | 663 unsigned NumOps = OldMI->getNumOperands();
664 for (unsigned I = 1; I < NumOps; ++I) {
683 unsigned NumOps = MI->getNumOperands();
717 for (unsigned I = 2; I < NumOps; ++I)
[all...] |
