/external/llvm/lib/Target/Hexagon/ |
HexagonExpandPredSpillCode.cpp | 101 MachineOperand &Op0 = MI->getOperand(0); 112 NewMI->addOperand(Op0); 144 MachineOperand &Op0 = MI->getOperand(0); 156 NewMI->addOperand(Op0); 186 MachineOperand &Op0 = MI->getOperand(0); 197 NewMI->addOperand(Op0); 223 MachineOperand &Op0 = MI->getOperand(0); 233 NewMI->addOperand(Op0);
|
HexagonPeephole.cpp | 247 MachineOperand &Op0 = MI->getOperand(0); 248 unsigned Reg0 = Op0.getReg(); 251 // Handle instructions that have a prediate register in op0
|
HexagonCopyToCombine.cpp | 120 const MachineOperand &Op0 = MI->getOperand(0); 122 assert(Op0.isReg() && Op1.isReg()); 124 unsigned DestReg = Op0.getReg(); 133 const MachineOperand &Op0 = MI->getOperand(0); 135 assert(Op0.isReg()); 137 unsigned DestReg = Op0.getReg();
|
HexagonGenPredicate.cpp | 396 MachineOperand &Op0 = MI->getOperand(0); 397 assert(Op0.isDef()); 398 Register OutR(Op0);
|
HexagonSplitDouble.cpp | 671 MachineOperand &Op0 = MI->getOperand(0); 673 assert(Op0.isReg() && Op1.isImm()); 678 UUPairMap::const_iterator F = PairMap.find(Op0.getReg()); 699 MachineOperand &Op0 = MI->getOperand(0); 702 assert(Op0.isReg()); 706 UUPairMap::const_iterator F = PairMap.find(Op0.getReg()); 732 MachineOperand &Op0 = MI->getOperand(0); 734 assert(Op0.isReg() && Op1.isReg()); 738 UUPairMap::const_iterator F = PairMap.find(Op0.getReg()); 753 MachineOperand &Op0 = MI->getOperand(0) [all...] |
/external/llvm/lib/ExecutionEngine/Interpreter/ |
Execution.cpp | [all...] |
/external/llvm/lib/Target/AArch64/Utils/ |
AArch64BaseInfo.cpp | 858 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name 867 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; 869 Ops[1].getAsInteger(10, Op0); 874 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; 899 uint32_t Op0 = (Bits >> 14) & 0x3; 905 return "s" + utostr(Op0)+ "_" + utostr(Op1) + "_c" + utostr(CRn)
|
/external/llvm/lib/Transforms/Scalar/ |
CorrelatedValuePropagation.cpp | 194 Value *Op0 = C->getOperand(0); 203 auto *I = dyn_cast<Instruction>(Op0); 208 LVI->getPredicateAt(C->getPredicate(), Op0, Op1, C); 346 Value *Op0 = C->getOperand(0); 351 LVI->getPredicateAt(C->getPredicate(), Op0, Op1, At);
|
Scalarizer.cpp | 74 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, 76 return Builder.CreateFCmp(FCI.getPredicate(), Op0, Op1, Name); 85 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, 87 return Builder.CreateICmp(ICI.getPredicate(), Op0, Op1, Name); 96 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, 98 return Builder.CreateBinOp(BO.getOpcode(), Op0, Op1, Name); 381 Scatterer Op0 = scatter(&I, I.getOperand(0)); 383 assert(Op0.size() == NumElems && "Mismatched binary operation"); 388 Res[Elem] = Split(Builder, Op0[Elem], Op1[Elem], 409 Scatterer Op0 = scatter(&SI, SI.getOperand(0)) [all...] |
/external/llvm/lib/CodeGen/ |
IntrinsicLowering.cpp | 496 Value *Op0 = CI->getArgOperand(0); 497 Type *IntPtr = DL.getIntPtrType(Op0->getType()); 501 Ops[0] = Op0;
|
/external/llvm/lib/Target/MSP430/ |
MSP430ISelDAGToDAG.cpp | 286 SDValue Op0, Op1; 290 if (!SelectAddr(Op, Op0, Op1)) 295 OutOps.push_back(Op0);
|
/external/llvm/lib/Target/Sparc/ |
SparcISelDAGToDAG.cpp | 390 SDValue Op0, Op1; 395 if (!SelectADDRrr(Op, Op0, Op1)) 396 SelectADDRri(Op, Op0, Op1); 400 OutOps.push_back(Op0);
|
/external/llvm/lib/IR/ |
AutoUpgrade.cpp | 568 Value *Op0 = CI->getArgOperand(0); 580 Rep = Builder.CreateShuffleVector(Op0, Op1, ConstantVector::get(Idxs)); 585 Value *Op0 = CI->getArgOperand(0); 626 Rep = Builder.CreateShuffleVector(Op0, Rep, ConstantVector::get(Idxs2)); 631 Value *Op0 = CI->getArgOperand(0); 646 Value *UndefV = UndefValue::get(Op0->getType()); 647 Rep = Builder.CreateShuffleVector(Op0, UndefV, ConstantVector::get(Idxs)); 660 Value *Op0 = CI->getArgOperand(0); 681 Rep = Builder.CreateShuffleVector(Op0, Op0, ConstantVector::get(Idxs)) [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
InstCombineShifts.cpp | 26 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); 33 if (isa<Constant>(Op0)) 39 if (Instruction *Res = FoldShiftByConstant(Op0, CUI, I)) 321 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1, 339 CanEvaluateShifted(Op0, COp1->getZExtValue(), isLeftShift, *this, &I)) { 341 " to eliminate shift:\n IN: " << *Op0 << "\n SH: " << I <<"\n"); 344 I, GetShiftedValue(Op0, COp1->getZExtValue(), isLeftShift, *this, DL)); 349 uint32_t TypeBits = Op0->getType()->getScalarSizeInBits(); 355 if (BinaryOperator *BO = dyn_cast<BinaryOperator>(Op0)) 362 if (SelectInst *SI = dyn_cast<SelectInst>(Op0)) [all...] |
InstCombineMulDivRem.cpp | 177 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); 182 if (Value *V = SimplifyMulInst(Op0, Op1, DL, TLI, DT, AC)) 190 BinaryOperator *BO = BinaryOperator::CreateNeg(Op0, I.getName()); 252 if (Op0->hasOneUse()) { 255 if (match(Op0, m_Sub(m_Value(Y), m_Value(X)))) 257 else if (match(Op0, m_Add(m_Value(Y), m_ConstantInt(C1)))) 271 if (SelectInst *SI = dyn_cast<SelectInst>(Op0)) 275 if (isa<PHINode>(Op0)) 283 if (match(Op0, m_OneUse(m_Add(m_Value(X), m_Constant(C1))))) { 293 if (Value *Op0v = dyn_castNegVal(Op0)) { // -X * -Y = X* [all...] |
/external/llvm/lib/Target/AArch64/InstPrinter/ |
AArch64InstPrinter.cpp | 66 const MCOperand &Op0 = MI->getOperand(0); 99 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg()) 135 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg()) 145 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg()) 153 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg()) 160 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0 172 O << "\tbfc\t" << getRegisterName(Op0.getReg()) 182 O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", " 192 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg() [all...] |
/external/llvm/lib/ExecutionEngine/ |
ExecutionEngine.cpp | 647 Constant *Op0 = CE->getOperand(0); 651 GenericValue Result = getConstantValue(Op0); 660 GenericValue GV = getConstantValue(Op0); 666 GenericValue GV = getConstantValue(Op0); 672 GenericValue GV = getConstantValue(Op0); 679 GenericValue GV = getConstantValue(Op0); 685 GenericValue GV = getConstantValue(Op0); 690 GenericValue GV = getConstantValue(Op0); 705 GenericValue GV = getConstantValue(Op0); 721 GenericValue GV = getConstantValue(Op0); [all...] |
/external/llvm/lib/Target/NVPTX/ |
NVPTXISelDAGToDAG.cpp | [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZISelDAGToDAG.cpp | 295 // If Op0 is null, then Node is a constant that can be loaded using: 299 // If Op0 is nonnull, then Node can be implemented using: 301 // (Opcode (Opcode Op0 UpperVal) LowerVal) 302 SDNode *splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0, 414 // The base or index of AM is equivalent to Op0 + Op1, where IsBase selects 417 SDValue Op0, uint64_t Op1) { 421 changeComponent(AM, IsBase, Op0); 440 SDValue Op0 = N.getOperand(0); 443 unsigned Op0Code = Op0->getOpcode(); 449 return expandAdjDynAlloc(AM, IsBase, Op0); [all...] |
SystemZISelLowering.cpp | 45 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {} 48 SDValue Op0, Op1; 50 // The opcode that should be used to compare Op0 and Op1. [all...] |
/external/llvm/lib/Target/X86/ |
X86FloatingPoint.cpp | [all...] |
X86MCInstLower.cpp | 323 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg(); 328 if (Op0 == X86::AX && Op1 == X86::AL) 332 if (Op0 == X86::EAX && Op1 == X86::AX) 336 if (Op0 == X86::RAX && Op1 == X86::EAX) [all...] |
/external/llvm/lib/CodeGen/AsmPrinter/ |
AsmPrinter.cpp | [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
FastISel.cpp | 422 unsigned Op0 = getRegForValue(I->getOperand(0)); 423 if (!Op0) // Unhandled operand. Halt "fast" selection and bail. 445 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, 458 ISDOpcode, Op0, Op0IsKill, CF); 473 ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill); [all...] |
LegalizeFloatTypes.cpp | [all...] |