| /external/llvm/lib/Target/BPF/MCTargetDesc/ |
| BPFMCCodeEmitter.cpp | 161 MCOperand Op2 = MI.getOperand(2);
162 assert(Op2.isImm() && "Second operand is not immediate.");
163 Encoding |= Op2.getImm() & 0xffff;
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 103 MachineOperand &Op2 = MI->getOperand(2);
119 NewMI->addOperand(Op2);
146 MachineOperand &Op2 = MI->getOperand(2);
157 NewMI->addOperand(Op2);
188 MachineOperand &Op2 = MI->getOperand(2);
198 NewMI->addOperand(Op2);
225 MachineOperand &Op2 = MI->getOperand(2);
239 NewMI->addOperand(Op2);
|
| HexagonPeephole.cpp | 291 MachineOperand Op2 = MI->getOperand(S2);
292 ChangeOpInto(MI->getOperand(S1), Op2);
|
| HexagonSplitDouble.cpp | 701 MachineOperand &Op2 = MI->getOperand(2);
719 if (Op2.isImm()) {
721 .addImm(Op2.getImm());
722 } else if (Op2.isReg()) {
724 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());
755 MachineOperand &Op2 = MI->getOperand(2);
756 assert(Op0.isReg() && Op1.isReg() && Op2.isImm());
757 int64_t Sh64 = Op2.getImm()
[all...] |
| HexagonHardwareLoops.cpp | 639 const MachineOperand &Op2 = CondI->getOperand(2);
643 if (Op2.isImm() || Op1.getReg() == IVReg)
644 EndValue = &Op2;
[all...] |
| HexagonISelLowering.cpp | [all...] |
| HexagonInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.cpp | 858 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
867 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
873 Ops[5].getAsInteger(10, Op2);
874 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
903 uint32_t Op2 = Bits & 0x7;
906 + "_c" + utostr(CRm) + "_" + utostr(Op2);
|
| /external/llvm/lib/Target/X86/ |
| X86OptimizeLEAs.cpp | 206 const MachineOperand *Op2 = &MI2.getOperand(N2 + X86::AddrDisp);
207 if (!isIdenticalOp(*Op1, *Op2)) {
208 if (Op1->isImm() && Op2->isImm())
209 AddrDispShift = Op1->getImm() - Op2->getImm();
210 else if (Op1->isGlobal() && Op2->isGlobal() &&
211 Op1->getGlobal() == Op2->getGlobal())
212 AddrDispShift = Op1->getOffset() - Op2->getOffset();
|
| X86ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
254 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
269 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
347 unsigned Op1, Op2;
348 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
353 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
360 unsigned Op1, Op2;
361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
366 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder)
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 68 const MCOperand &Op2 = MI->getOperand(2);
73 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
109 if (Op2.isImm() && Op3.isImm()) {
112 int64_t immr = Op2.getImm();
143 if (Op2.getImm() > Op3.getImm()) {
146 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
154 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
161 const MCOperand &Op2 = MI->getOperand(2)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 324 const MachineOperand &Op2 = I->getOperand(2);
326 if ((Op1.isReg() && Op1.isUndef()) || (Op2.isReg() && Op2.isUndef())) {
349 unsigned N = Op2.getImm();
[all...] |
| MipsSEISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Scalarizer.cpp | 402 Scatterer Op2 = scatter(&SI, SI.getOperand(2));
404 assert(Op2.size() == NumElems && "Mismatched select");
412 Res[I] = Builder.CreateSelect(Op0[I], Op1[I], Op2[I],
417 Res[I] = Builder.CreateSelect(Op0, Op1[I], Op2[I],
|
| LoopRerollPass.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 736 SDValue Op2 = Op.getOperand(2);
739 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
773 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
780 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
781 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
[all...] |
| LegalizeFloatTypes.cpp | [all...] |
| TargetLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetInstrInfo.cpp | 566 const MachineOperand &Op2 = Inst.getOperand(2);
575 if (Op2.isReg() && TargetRegisterInfo::isVirtualRegister(Op2.getReg()))
576 MI2 = MRI.getUniqueVRegDef(Op2.getReg());
[all...] |
| /external/llvm/lib/Analysis/ |
| CFLAliasAnalysis.cpp | 185 auto *Op2 = Inst.getOperand(1);
187 Output.push_back(Edge(&Inst, Op2, EdgeType::Assign, AttrNone));
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 178 ICToken Op2 = OperandStack.pop_back_val();
185 Val = Op1.second + Op2.second;
189 Val = Op1.second - Op2.second;
193 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
195 Val = Op1.second * Op2.second;
199 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
201 assert (Op2.second != 0 && "Division by zero!");
202 Val = Op1.second / Op2.second;
206 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
208 Val = Op1.second | Op2.second
[all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_2_7/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 117 unsigned Op2, bool Op2IsKill);
338 unsigned Op2, bool Op2IsKill) {
346 Op2 = constrainOperandRegClass(II, Op1, 3);
353 .addReg(Op2, Op2IsKill * RegState::Kill));
358 .addReg(Op2, Op2IsKill * RegState::Kill));
[all...] |
