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    Searched defs:RS1 (Results 1 - 2 of 2) sorted by null

  /toolchain/binutils/binutils-2.25/include/opcode/
sparc.h 178 1 rs1 register.
197 M alternate space register (asr) in rs1
221 r Single register that is both rs1 and rd.
229 U sparclet coprocessor registers in rs1 position
241 ? Privileged Register in rs1 (v9)
246 / Ancillary state register in rs1 (v9a)
268 #define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
278 #define RS1_G0 RS1 (~0)
  /external/llvm/lib/Target/Hexagon/
HexagonSplitDouble.cpp 895 unsigned RS1 = getRegState(Op1);
919 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
922 .addReg(Op1.getReg(), RS1, HiSR)
926 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
936 .addReg(Op1.getReg(), RS1, HiSR)
948 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
950 .addReg(Op1.getReg(), RS1, HiSR)
959 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
961 .addReg(Op1.getReg(), RS1, HiSR)
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