| /external/valgrind/none/tests/mips64/ |
| shift_instructions.c | 10 SRA, SRAV, SRL, SRLV
189 case SRL:
190 TEST2("srl $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
191 TEST2("srl $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
192 TEST2("srl $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
193 TEST2("srl $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZSelectionDAGInfo.cpp | 179 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i32, IPM,
181 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL,
|
| /external/llvm/include/llvm/TableGen/ |
| Record.h | 727 enum BinaryOp { ADD, AND, SHL, SRA, SRL, LISTCONCAT, STRCONCAT, CONCAT, EQ };
[all...] |
| /external/pcre/dist/sljit/ |
| sljitNativeMIPS_common.c | 167 #define SRL (HI(0) | LO(2))
[all...] |
| sljitNativeSPARC_common.c | 154 #define SRL (OPC1(0x2) | OPC3(0x26))
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | 398 case LSR: mMips->SRL(tmpReg, amode.reg, amode.value); break;
509 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break;
541 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break;
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 336 SHL, SRA, SRL, ROTL, ROTR,
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 690 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
699 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
| /external/v8/src/s390/ |
| constants-s390.h | [all...] |
