/external/llvm/lib/Target/WebAssembly/ |
WebAssemblyLowerBrUnless.cpp | 109 unsigned ZeroReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass); 110 MFI.stackifyVReg(ZeroReg); 111 BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::CONST_I32), ZeroReg) 117 .addReg(ZeroReg);
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/external/llvm/lib/Target/Mips/ |
MipsSEInstrInfo.cpp | 83 unsigned Opc = 0, ZeroReg = 0; 91 Opc = Mips::OR, ZeroReg = Mips::ZERO; 144 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; 175 if (ZeroReg) 176 MIB.addReg(ZeroReg); 457 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 476 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
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MipsAsmPrinter.cpp | 122 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; 123 TmpInst0.addOperand(MCOperand::createReg(ZeroReg)); [all...] |
MipsSEISelDAGToDAG.cpp | 88 unsigned DstReg = 0, ZeroReg = 0; 95 ZeroReg = Mips::ZERO; 100 ZeroReg = Mips::ZERO_64; 106 // Replace uses with ZeroReg. 120 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg)) 123 MO.setReg(ZeroReg); [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCInstrInfo.cpp | [all...] |
PPCISelLowering.cpp | [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64FastISel.cpp | 346 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; 349 ResultReg).addReg(ZeroReg, getKillRegState(true)); [all...] |
/external/llvm/lib/Target/ARM/ |
ARMFastISel.cpp | [all...] |
/external/llvm/lib/Target/Mips/AsmParser/ |
MipsAsmParser.cpp | [all...] |