1 //===-- SparcMCCodeEmitter.cpp - Convert Sparc code to machine code -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the SparcMCCodeEmitter class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "SparcMCExpr.h" 15 #include "MCTargetDesc/SparcFixupKinds.h" 16 #include "SparcMCTargetDesc.h" 17 #include "llvm/ADT/Statistic.h" 18 #include "llvm/MC/MCCodeEmitter.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSymbol.h" 24 #include "llvm/MC/MCAsmInfo.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 using namespace llvm; 28 29 #define DEBUG_TYPE "mccodeemitter" 30 31 STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); 32 33 namespace { 34 class SparcMCCodeEmitter : public MCCodeEmitter { 35 SparcMCCodeEmitter(const SparcMCCodeEmitter &) = delete; 36 void operator=(const SparcMCCodeEmitter &) = delete; 37 MCContext &Ctx; 38 39 public: 40 SparcMCCodeEmitter(MCContext &ctx): Ctx(ctx) {} 41 42 ~SparcMCCodeEmitter() override {} 43 44 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 45 SmallVectorImpl<MCFixup> &Fixups, 46 const MCSubtargetInfo &STI) const override; 47 48 // getBinaryCodeForInstr - TableGen'erated function for getting the 49 // binary encoding for an instruction. 50 uint64_t getBinaryCodeForInstr(const MCInst &MI, 51 SmallVectorImpl<MCFixup> &Fixups, 52 const MCSubtargetInfo &STI) const; 53 54 /// getMachineOpValue - Return binary encoding of operand. If the machine 55 /// operand requires relocation, record the relocation and return zero. 56 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 57 SmallVectorImpl<MCFixup> &Fixups, 58 const MCSubtargetInfo &STI) const; 59 60 unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo, 61 SmallVectorImpl<MCFixup> &Fixups, 62 const MCSubtargetInfo &STI) const; 63 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, 64 SmallVectorImpl<MCFixup> &Fixups, 65 const MCSubtargetInfo &STI) const; 66 unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo, 67 SmallVectorImpl<MCFixup> &Fixups, 68 const MCSubtargetInfo &STI) const; 69 unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo, 70 SmallVectorImpl<MCFixup> &Fixups, 71 const MCSubtargetInfo &STI) const; 72 73 }; 74 } // end anonymous namespace 75 76 MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII, 77 const MCRegisterInfo &MRI, 78 MCContext &Ctx) { 79 return new SparcMCCodeEmitter(Ctx); 80 } 81 82 void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, 83 SmallVectorImpl<MCFixup> &Fixups, 84 const MCSubtargetInfo &STI) const { 85 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI); 86 87 if (Ctx.getAsmInfo()->isLittleEndian()) { 88 // Output the bits in little-endian byte order. 89 support::endian::Writer<support::little>(OS).write<uint32_t>(Bits); 90 } else { 91 // Output the bits in big-endian byte order. 92 support::endian::Writer<support::big>(OS).write<uint32_t>(Bits); 93 } 94 unsigned tlsOpNo = 0; 95 switch (MI.getOpcode()) { 96 default: break; 97 case SP::TLS_CALL: tlsOpNo = 1; break; 98 case SP::TLS_ADDrr: 99 case SP::TLS_ADDXrr: 100 case SP::TLS_LDrr: 101 case SP::TLS_LDXrr: tlsOpNo = 3; break; 102 } 103 if (tlsOpNo != 0) { 104 const MCOperand &MO = MI.getOperand(tlsOpNo); 105 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI); 106 assert(op == 0 && "Unexpected operand value!"); 107 (void)op; // suppress warning. 108 } 109 110 ++MCNumEmitted; // Keep track of the # of mi's emitted. 111 } 112 113 114 unsigned SparcMCCodeEmitter:: 115 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 116 SmallVectorImpl<MCFixup> &Fixups, 117 const MCSubtargetInfo &STI) const { 118 119 if (MO.isReg()) 120 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); 121 122 if (MO.isImm()) 123 return MO.getImm(); 124 125 assert(MO.isExpr()); 126 const MCExpr *Expr = MO.getExpr(); 127 if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) { 128 MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind(); 129 Fixups.push_back(MCFixup::create(0, Expr, Kind)); 130 return 0; 131 } 132 133 int64_t Res; 134 if (Expr->evaluateAsAbsolute(Res)) 135 return Res; 136 137 llvm_unreachable("Unhandled expression!"); 138 return 0; 139 } 140 141 unsigned SparcMCCodeEmitter:: 142 getCallTargetOpValue(const MCInst &MI, unsigned OpNo, 143 SmallVectorImpl<MCFixup> &Fixups, 144 const MCSubtargetInfo &STI) const { 145 const MCOperand &MO = MI.getOperand(OpNo); 146 if (MO.isReg() || MO.isImm()) 147 return getMachineOpValue(MI, MO, Fixups, STI); 148 149 if (MI.getOpcode() == SP::TLS_CALL) { 150 // No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in 151 // encodeInstruction. 152 #ifndef NDEBUG 153 // Verify that the callee is actually __tls_get_addr. 154 const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr()); 155 assert(SExpr && SExpr->getSubExpr()->getKind() == MCExpr::SymbolRef && 156 "Unexpected expression in TLS_CALL"); 157 const MCSymbolRefExpr *SymExpr = cast<MCSymbolRefExpr>(SExpr->getSubExpr()); 158 assert(SymExpr->getSymbol().getName() == "__tls_get_addr" && 159 "Unexpected function for TLS_CALL"); 160 #endif 161 return 0; 162 } 163 164 MCFixupKind fixupKind = (MCFixupKind)Sparc::fixup_sparc_call30; 165 166 if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr())) { 167 if (SExpr->getKind() == SparcMCExpr::VK_Sparc_WPLT30) 168 fixupKind = (MCFixupKind)Sparc::fixup_sparc_wplt30; 169 } 170 171 Fixups.push_back(MCFixup::create(0, MO.getExpr(), fixupKind)); 172 173 return 0; 174 } 175 176 unsigned SparcMCCodeEmitter:: 177 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, 178 SmallVectorImpl<MCFixup> &Fixups, 179 const MCSubtargetInfo &STI) const { 180 const MCOperand &MO = MI.getOperand(OpNo); 181 if (MO.isReg() || MO.isImm()) 182 return getMachineOpValue(MI, MO, Fixups, STI); 183 184 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 185 (MCFixupKind)Sparc::fixup_sparc_br22)); 186 return 0; 187 } 188 189 unsigned SparcMCCodeEmitter:: 190 getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo, 191 SmallVectorImpl<MCFixup> &Fixups, 192 const MCSubtargetInfo &STI) const { 193 const MCOperand &MO = MI.getOperand(OpNo); 194 if (MO.isReg() || MO.isImm()) 195 return getMachineOpValue(MI, MO, Fixups, STI); 196 197 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 198 (MCFixupKind)Sparc::fixup_sparc_br19)); 199 return 0; 200 } 201 unsigned SparcMCCodeEmitter:: 202 getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo, 203 SmallVectorImpl<MCFixup> &Fixups, 204 const MCSubtargetInfo &STI) const { 205 const MCOperand &MO = MI.getOperand(OpNo); 206 if (MO.isReg() || MO.isImm()) 207 return getMachineOpValue(MI, MO, Fixups, STI); 208 209 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 210 (MCFixupKind)Sparc::fixup_sparc_br16_2)); 211 Fixups.push_back(MCFixup::create(0, MO.getExpr(), 212 (MCFixupKind)Sparc::fixup_sparc_br16_14)); 213 214 return 0; 215 } 216 217 218 219 #include "SparcGenMCCodeEmitter.inc" 220
