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      1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file provides Mips specific target streamer methods.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "InstPrinter/MipsInstPrinter.h"
     15 #include "MipsELFStreamer.h"
     16 #include "MipsMCTargetDesc.h"
     17 #include "MipsTargetObjectFile.h"
     18 #include "MipsTargetStreamer.h"
     19 #include "llvm/MC/MCContext.h"
     20 #include "llvm/MC/MCSectionELF.h"
     21 #include "llvm/MC/MCSubtargetInfo.h"
     22 #include "llvm/MC/MCSymbolELF.h"
     23 #include "llvm/Support/CommandLine.h"
     24 #include "llvm/Support/ELF.h"
     25 #include "llvm/Support/ErrorHandling.h"
     26 #include "llvm/Support/FormattedStream.h"
     27 
     28 using namespace llvm;
     29 
     30 MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
     31     : MCTargetStreamer(S), ModuleDirectiveAllowed(true) {
     32   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
     33 }
     34 void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
     35 void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
     36 void MipsTargetStreamer::emitDirectiveSetMips16() {}
     37 void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); }
     38 void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
     39 void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
     40 void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
     41 void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
     42 void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
     43 void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
     44 void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
     45 void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
     46   forbidModuleDirective();
     47 }
     48 void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
     49 void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
     50 void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
     51 void MipsTargetStreamer::emitDirectiveAbiCalls() {}
     52 void MipsTargetStreamer::emitDirectiveNaN2008() {}
     53 void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
     54 void MipsTargetStreamer::emitDirectiveOptionPic0() {}
     55 void MipsTargetStreamer::emitDirectiveOptionPic2() {}
     56 void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
     57 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
     58                                    unsigned ReturnReg) {}
     59 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
     60 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
     61 }
     62 void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
     63   forbidModuleDirective();
     64 }
     65 void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
     66 void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
     67 void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
     68 void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
     69 void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
     70 void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
     71 void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
     72 void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
     73 void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
     74 void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
     75 void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
     76 void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
     77 void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
     78 void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
     79 void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
     80 void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
     81 void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
     82 void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
     83 void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
     84   forbidModuleDirective();
     85 }
     86 void MipsTargetStreamer::emitDirectiveSetHardFloat() {
     87   forbidModuleDirective();
     88 }
     89 void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
     90 void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
     91 void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
     92 void MipsTargetStreamer::emitDirectiveCpRestore(
     93     SmallVector<MCInst, 3> &StoreInsts, int Offset) {
     94   forbidModuleDirective();
     95 }
     96 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
     97                                               const MCSymbol &Sym, bool IsReg) {
     98 }
     99 void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
    100                                                bool SaveLocationIsRegister) {}
    101 
    102 void MipsTargetStreamer::emitDirectiveModuleFP() {}
    103 
    104 void MipsTargetStreamer::emitDirectiveModuleOddSPReg() {
    105   if (!ABIFlagsSection.OddSPReg && !ABIFlagsSection.Is32BitABI)
    106     report_fatal_error("+nooddspreg is only valid for O32");
    107 }
    108 void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
    109 void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
    110 void MipsTargetStreamer::emitDirectiveSetFp(
    111     MipsABIFlagsSection::FpABIKind Value) {
    112   forbidModuleDirective();
    113 }
    114 void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
    115 void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
    116   forbidModuleDirective();
    117 }
    118 
    119 MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
    120                                              formatted_raw_ostream &OS)
    121     : MipsTargetStreamer(S), OS(OS) {}
    122 
    123 void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() {
    124   OS << "\t.set\tmicromips\n";
    125   forbidModuleDirective();
    126 }
    127 
    128 void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() {
    129   OS << "\t.set\tnomicromips\n";
    130   forbidModuleDirective();
    131 }
    132 
    133 void MipsTargetAsmStreamer::emitDirectiveSetMips16() {
    134   OS << "\t.set\tmips16\n";
    135   forbidModuleDirective();
    136 }
    137 
    138 void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() {
    139   OS << "\t.set\tnomips16\n";
    140   MipsTargetStreamer::emitDirectiveSetNoMips16();
    141 }
    142 
    143 void MipsTargetAsmStreamer::emitDirectiveSetReorder() {
    144   OS << "\t.set\treorder\n";
    145   MipsTargetStreamer::emitDirectiveSetReorder();
    146 }
    147 
    148 void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() {
    149   OS << "\t.set\tnoreorder\n";
    150   forbidModuleDirective();
    151 }
    152 
    153 void MipsTargetAsmStreamer::emitDirectiveSetMacro() {
    154   OS << "\t.set\tmacro\n";
    155   MipsTargetStreamer::emitDirectiveSetMacro();
    156 }
    157 
    158 void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() {
    159   OS << "\t.set\tnomacro\n";
    160   MipsTargetStreamer::emitDirectiveSetNoMacro();
    161 }
    162 
    163 void MipsTargetAsmStreamer::emitDirectiveSetMsa() {
    164   OS << "\t.set\tmsa\n";
    165   MipsTargetStreamer::emitDirectiveSetMsa();
    166 }
    167 
    168 void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() {
    169   OS << "\t.set\tnomsa\n";
    170   MipsTargetStreamer::emitDirectiveSetNoMsa();
    171 }
    172 
    173 void MipsTargetAsmStreamer::emitDirectiveSetAt() {
    174   OS << "\t.set\tat\n";
    175   MipsTargetStreamer::emitDirectiveSetAt();
    176 }
    177 
    178 void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
    179   OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
    180   MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);
    181 }
    182 
    183 void MipsTargetAsmStreamer::emitDirectiveSetNoAt() {
    184   OS << "\t.set\tnoat\n";
    185   MipsTargetStreamer::emitDirectiveSetNoAt();
    186 }
    187 
    188 void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) {
    189   OS << "\t.end\t" << Name << '\n';
    190 }
    191 
    192 void MipsTargetAsmStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
    193   OS << "\t.ent\t" << Symbol.getName() << '\n';
    194 }
    195 
    196 void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
    197 
    198 void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
    199 
    200 void MipsTargetAsmStreamer::emitDirectiveNaNLegacy() {
    201   OS << "\t.nan\tlegacy\n";
    202 }
    203 
    204 void MipsTargetAsmStreamer::emitDirectiveOptionPic0() {
    205   OS << "\t.option\tpic0\n";
    206 }
    207 
    208 void MipsTargetAsmStreamer::emitDirectiveOptionPic2() {
    209   OS << "\t.option\tpic2\n";
    210 }
    211 
    212 void MipsTargetAsmStreamer::emitDirectiveInsn() {
    213   MipsTargetStreamer::emitDirectiveInsn();
    214   OS << "\t.insn\n";
    215 }
    216 
    217 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
    218                                       unsigned ReturnReg) {
    219   OS << "\t.frame\t$"
    220      << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
    221      << StackSize << ",$"
    222      << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
    223 }
    224 
    225 void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
    226   OS << "\t.set arch=" << Arch << "\n";
    227   MipsTargetStreamer::emitDirectiveSetArch(Arch);
    228 }
    229 
    230 void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
    231   OS << "\t.set\tmips0\n";
    232   MipsTargetStreamer::emitDirectiveSetMips0();
    233 }
    234 
    235 void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
    236   OS << "\t.set\tmips1\n";
    237   MipsTargetStreamer::emitDirectiveSetMips1();
    238 }
    239 
    240 void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
    241   OS << "\t.set\tmips2\n";
    242   MipsTargetStreamer::emitDirectiveSetMips2();
    243 }
    244 
    245 void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
    246   OS << "\t.set\tmips3\n";
    247   MipsTargetStreamer::emitDirectiveSetMips3();
    248 }
    249 
    250 void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
    251   OS << "\t.set\tmips4\n";
    252   MipsTargetStreamer::emitDirectiveSetMips4();
    253 }
    254 
    255 void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
    256   OS << "\t.set\tmips5\n";
    257   MipsTargetStreamer::emitDirectiveSetMips5();
    258 }
    259 
    260 void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
    261   OS << "\t.set\tmips32\n";
    262   MipsTargetStreamer::emitDirectiveSetMips32();
    263 }
    264 
    265 void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
    266   OS << "\t.set\tmips32r2\n";
    267   MipsTargetStreamer::emitDirectiveSetMips32R2();
    268 }
    269 
    270 void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
    271   OS << "\t.set\tmips32r3\n";
    272   MipsTargetStreamer::emitDirectiveSetMips32R3();
    273 }
    274 
    275 void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
    276   OS << "\t.set\tmips32r5\n";
    277   MipsTargetStreamer::emitDirectiveSetMips32R5();
    278 }
    279 
    280 void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
    281   OS << "\t.set\tmips32r6\n";
    282   MipsTargetStreamer::emitDirectiveSetMips32R6();
    283 }
    284 
    285 void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
    286   OS << "\t.set\tmips64\n";
    287   MipsTargetStreamer::emitDirectiveSetMips64();
    288 }
    289 
    290 void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
    291   OS << "\t.set\tmips64r2\n";
    292   MipsTargetStreamer::emitDirectiveSetMips64R2();
    293 }
    294 
    295 void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
    296   OS << "\t.set\tmips64r3\n";
    297   MipsTargetStreamer::emitDirectiveSetMips64R3();
    298 }
    299 
    300 void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
    301   OS << "\t.set\tmips64r5\n";
    302   MipsTargetStreamer::emitDirectiveSetMips64R5();
    303 }
    304 
    305 void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
    306   OS << "\t.set\tmips64r6\n";
    307   MipsTargetStreamer::emitDirectiveSetMips64R6();
    308 }
    309 
    310 void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
    311   OS << "\t.set\tdsp\n";
    312   MipsTargetStreamer::emitDirectiveSetDsp();
    313 }
    314 
    315 void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
    316   OS << "\t.set\tnodsp\n";
    317   MipsTargetStreamer::emitDirectiveSetNoDsp();
    318 }
    319 
    320 void MipsTargetAsmStreamer::emitDirectiveSetPop() {
    321   OS << "\t.set\tpop\n";
    322   MipsTargetStreamer::emitDirectiveSetPop();
    323 }
    324 
    325 void MipsTargetAsmStreamer::emitDirectiveSetPush() {
    326  OS << "\t.set\tpush\n";
    327  MipsTargetStreamer::emitDirectiveSetPush();
    328 }
    329 
    330 void MipsTargetAsmStreamer::emitDirectiveSetSoftFloat() {
    331   OS << "\t.set\tsoftfloat\n";
    332   MipsTargetStreamer::emitDirectiveSetSoftFloat();
    333 }
    334 
    335 void MipsTargetAsmStreamer::emitDirectiveSetHardFloat() {
    336   OS << "\t.set\thardfloat\n";
    337   MipsTargetStreamer::emitDirectiveSetHardFloat();
    338 }
    339 
    340 // Print a 32 bit hex number with all numbers.
    341 static void printHex32(unsigned Value, raw_ostream &OS) {
    342   OS << "0x";
    343   for (int i = 7; i >= 0; i--)
    344     OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
    345 }
    346 
    347 void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
    348                                      int CPUTopSavedRegOff) {
    349   OS << "\t.mask \t";
    350   printHex32(CPUBitmask, OS);
    351   OS << ',' << CPUTopSavedRegOff << '\n';
    352 }
    353 
    354 void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
    355                                       int FPUTopSavedRegOff) {
    356   OS << "\t.fmask\t";
    357   printHex32(FPUBitmask, OS);
    358   OS << "," << FPUTopSavedRegOff << '\n';
    359 }
    360 
    361 void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) {
    362   OS << "\t.cpload\t$"
    363      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
    364   forbidModuleDirective();
    365 }
    366 
    367 void MipsTargetAsmStreamer::emitDirectiveCpRestore(
    368     SmallVector<MCInst, 3> &StoreInsts, int Offset) {
    369   MipsTargetStreamer::emitDirectiveCpRestore(StoreInsts, Offset);
    370   OS << "\t.cprestore\t" << Offset << "\n";
    371 }
    372 
    373 void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
    374                                                  int RegOrOffset,
    375                                                  const MCSymbol &Sym,
    376                                                  bool IsReg) {
    377   OS << "\t.cpsetup\t$"
    378      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
    379 
    380   if (IsReg)
    381     OS << "$"
    382        << StringRef(MipsInstPrinter::getRegisterName(RegOrOffset)).lower();
    383   else
    384     OS << RegOrOffset;
    385 
    386   OS << ", ";
    387 
    388   OS << Sym.getName();
    389   forbidModuleDirective();
    390 }
    391 
    392 void MipsTargetAsmStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
    393                                                   bool SaveLocationIsRegister) {
    394   OS << "\t.cpreturn";
    395   forbidModuleDirective();
    396 }
    397 
    398 void MipsTargetAsmStreamer::emitDirectiveModuleFP() {
    399   OS << "\t.module\tfp=";
    400   OS << ABIFlagsSection.getFpABIString(ABIFlagsSection.getFpABI()) << "\n";
    401 }
    402 
    403 void MipsTargetAsmStreamer::emitDirectiveSetFp(
    404     MipsABIFlagsSection::FpABIKind Value) {
    405   MipsTargetStreamer::emitDirectiveSetFp(Value);
    406 
    407   OS << "\t.set\tfp=";
    408   OS << ABIFlagsSection.getFpABIString(Value) << "\n";
    409 }
    410 
    411 void MipsTargetAsmStreamer::emitDirectiveModuleOddSPReg() {
    412   MipsTargetStreamer::emitDirectiveModuleOddSPReg();
    413 
    414   OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
    415 }
    416 
    417 void MipsTargetAsmStreamer::emitDirectiveSetOddSPReg() {
    418   MipsTargetStreamer::emitDirectiveSetOddSPReg();
    419   OS << "\t.set\toddspreg\n";
    420 }
    421 
    422 void MipsTargetAsmStreamer::emitDirectiveSetNoOddSPReg() {
    423   MipsTargetStreamer::emitDirectiveSetNoOddSPReg();
    424   OS << "\t.set\tnooddspreg\n";
    425 }
    426 
    427 void MipsTargetAsmStreamer::emitDirectiveModuleSoftFloat() {
    428   OS << "\t.module\tsoftfloat\n";
    429 }
    430 
    431 void MipsTargetAsmStreamer::emitDirectiveModuleHardFloat() {
    432   OS << "\t.module\thardfloat\n";
    433 }
    434 
    435 // This part is for ELF object output.
    436 MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
    437                                              const MCSubtargetInfo &STI)
    438     : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
    439   MCAssembler &MCA = getStreamer().getAssembler();
    440   Pic = MCA.getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_;
    441 
    442   const FeatureBitset &Features = STI.getFeatureBits();
    443 
    444   // Set the header flags that we can in the constructor.
    445   // FIXME: This is a fairly terrible hack. We set the rest
    446   // of these in the destructor. The problem here is two-fold:
    447   //
    448   // a: Some of the eflags can be set/reset by directives.
    449   // b: There aren't any usage paths that initialize the ABI
    450   //    pointer until after we initialize either an assembler
    451   //    or the target machine.
    452   // We can fix this by making the target streamer construct
    453   // the ABI, but this is fraught with wide ranging dependency
    454   // issues as well.
    455   unsigned EFlags = MCA.getELFHeaderEFlags();
    456 
    457   // Architecture
    458   if (Features[Mips::FeatureMips64r6])
    459     EFlags |= ELF::EF_MIPS_ARCH_64R6;
    460   else if (Features[Mips::FeatureMips64r2] ||
    461            Features[Mips::FeatureMips64r3] ||
    462            Features[Mips::FeatureMips64r5])
    463     EFlags |= ELF::EF_MIPS_ARCH_64R2;
    464   else if (Features[Mips::FeatureMips64])
    465     EFlags |= ELF::EF_MIPS_ARCH_64;
    466   else if (Features[Mips::FeatureMips5])
    467     EFlags |= ELF::EF_MIPS_ARCH_5;
    468   else if (Features[Mips::FeatureMips4])
    469     EFlags |= ELF::EF_MIPS_ARCH_4;
    470   else if (Features[Mips::FeatureMips3])
    471     EFlags |= ELF::EF_MIPS_ARCH_3;
    472   else if (Features[Mips::FeatureMips32r6])
    473     EFlags |= ELF::EF_MIPS_ARCH_32R6;
    474   else if (Features[Mips::FeatureMips32r2] ||
    475            Features[Mips::FeatureMips32r3] ||
    476            Features[Mips::FeatureMips32r5])
    477     EFlags |= ELF::EF_MIPS_ARCH_32R2;
    478   else if (Features[Mips::FeatureMips32])
    479     EFlags |= ELF::EF_MIPS_ARCH_32;
    480   else if (Features[Mips::FeatureMips2])
    481     EFlags |= ELF::EF_MIPS_ARCH_2;
    482   else
    483     EFlags |= ELF::EF_MIPS_ARCH_1;
    484 
    485   // Other options.
    486   if (Features[Mips::FeatureNaN2008])
    487     EFlags |= ELF::EF_MIPS_NAN2008;
    488 
    489   // -mabicalls and -mplt are not implemented but we should act as if they were
    490   // given.
    491   EFlags |= ELF::EF_MIPS_CPIC;
    492 
    493   MCA.setELFHeaderEFlags(EFlags);
    494 }
    495 
    496 void MipsTargetELFStreamer::emitLabel(MCSymbol *S) {
    497   auto *Symbol = cast<MCSymbolELF>(S);
    498   if (!isMicroMipsEnabled())
    499     return;
    500   getStreamer().getAssembler().registerSymbol(*Symbol);
    501   uint8_t Type = Symbol->getType();
    502   if (Type != ELF::STT_FUNC)
    503     return;
    504 
    505   Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
    506 }
    507 
    508 void MipsTargetELFStreamer::finish() {
    509   MCAssembler &MCA = getStreamer().getAssembler();
    510   const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
    511 
    512   // .bss, .text and .data are always at least 16-byte aligned.
    513   MCSection &TextSection = *OFI.getTextSection();
    514   MCA.registerSection(TextSection);
    515   MCSection &DataSection = *OFI.getDataSection();
    516   MCA.registerSection(DataSection);
    517   MCSection &BSSSection = *OFI.getBSSSection();
    518   MCA.registerSection(BSSSection);
    519 
    520   TextSection.setAlignment(std::max(16u, TextSection.getAlignment()));
    521   DataSection.setAlignment(std::max(16u, DataSection.getAlignment()));
    522   BSSSection.setAlignment(std::max(16u, BSSSection.getAlignment()));
    523 
    524   const FeatureBitset &Features = STI.getFeatureBits();
    525 
    526   // Update e_header flags. See the FIXME and comment above in
    527   // the constructor for a full rundown on this.
    528   unsigned EFlags = MCA.getELFHeaderEFlags();
    529 
    530   // ABI
    531   // N64 does not require any ABI bits.
    532   if (getABI().IsO32())
    533     EFlags |= ELF::EF_MIPS_ABI_O32;
    534   else if (getABI().IsN32())
    535     EFlags |= ELF::EF_MIPS_ABI2;
    536 
    537   if (Features[Mips::FeatureGP64Bit]) {
    538     if (getABI().IsO32())
    539       EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
    540   } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
    541     EFlags |= ELF::EF_MIPS_32BITMODE;
    542 
    543   // If we've set the cpic eflag and we're n64, go ahead and set the pic
    544   // one as well.
    545   if (EFlags & ELF::EF_MIPS_CPIC && getABI().IsN64())
    546     EFlags |= ELF::EF_MIPS_PIC;
    547 
    548   MCA.setELFHeaderEFlags(EFlags);
    549 
    550   // Emit all the option records.
    551   // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
    552   // .reginfo.
    553   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
    554   MEF.EmitMipsOptionRecords();
    555 
    556   emitMipsAbiFlags();
    557 }
    558 
    559 void MipsTargetELFStreamer::emitAssignment(MCSymbol *S, const MCExpr *Value) {
    560   auto *Symbol = cast<MCSymbolELF>(S);
    561   // If on rhs is micromips symbol then mark Symbol as microMips.
    562   if (Value->getKind() != MCExpr::SymbolRef)
    563     return;
    564   const auto &RhsSym = cast<MCSymbolELF>(
    565       static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
    566 
    567   if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
    568     return;
    569 
    570   Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
    571 }
    572 
    573 MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
    574   return static_cast<MCELFStreamer &>(Streamer);
    575 }
    576 
    577 void MipsTargetELFStreamer::emitDirectiveSetMicroMips() {
    578   MicroMipsEnabled = true;
    579 
    580   MCAssembler &MCA = getStreamer().getAssembler();
    581   unsigned Flags = MCA.getELFHeaderEFlags();
    582   Flags |= ELF::EF_MIPS_MICROMIPS;
    583   MCA.setELFHeaderEFlags(Flags);
    584   forbidModuleDirective();
    585 }
    586 
    587 void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() {
    588   MicroMipsEnabled = false;
    589   forbidModuleDirective();
    590 }
    591 
    592 void MipsTargetELFStreamer::emitDirectiveSetMips16() {
    593   MCAssembler &MCA = getStreamer().getAssembler();
    594   unsigned Flags = MCA.getELFHeaderEFlags();
    595   Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
    596   MCA.setELFHeaderEFlags(Flags);
    597   forbidModuleDirective();
    598 }
    599 
    600 void MipsTargetELFStreamer::emitDirectiveSetNoReorder() {
    601   MCAssembler &MCA = getStreamer().getAssembler();
    602   unsigned Flags = MCA.getELFHeaderEFlags();
    603   Flags |= ELF::EF_MIPS_NOREORDER;
    604   MCA.setELFHeaderEFlags(Flags);
    605   forbidModuleDirective();
    606 }
    607 
    608 void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) {
    609   MCAssembler &MCA = getStreamer().getAssembler();
    610   MCContext &Context = MCA.getContext();
    611   MCStreamer &OS = getStreamer();
    612 
    613   MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS,
    614                                             ELF::SHF_ALLOC | ELF::SHT_REL);
    615 
    616   MCSymbol *Sym = Context.getOrCreateSymbol(Name);
    617   const MCSymbolRefExpr *ExprRef =
    618       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Context);
    619 
    620   MCA.registerSection(*Sec);
    621   Sec->setAlignment(4);
    622 
    623   OS.PushSection();
    624 
    625   OS.SwitchSection(Sec);
    626 
    627   OS.EmitValueImpl(ExprRef, 4);
    628 
    629   OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
    630   OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4);  // reg_offset
    631 
    632   OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
    633   OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4);  // fpreg_offset
    634 
    635   OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
    636   OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4);    // frame_reg
    637   OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4);   // return_reg
    638 
    639   // The .end directive marks the end of a procedure. Invalidate
    640   // the information gathered up until this point.
    641   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
    642 
    643   OS.PopSection();
    644 
    645   // .end also implicitly sets the size.
    646   MCSymbol *CurPCSym = Context.createTempSymbol();
    647   OS.EmitLabel(CurPCSym);
    648   const MCExpr *Size = MCBinaryExpr::createSub(
    649       MCSymbolRefExpr::create(CurPCSym, MCSymbolRefExpr::VK_None, Context),
    650       ExprRef, Context);
    651   int64_t AbsSize;
    652   if (!Size->evaluateAsAbsolute(AbsSize, MCA))
    653     llvm_unreachable("Function size must be evaluatable as absolute");
    654   Size = MCConstantExpr::create(AbsSize, Context);
    655   static_cast<MCSymbolELF *>(Sym)->setSize(Size);
    656 }
    657 
    658 void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
    659   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
    660 
    661   // .ent also acts like an implicit '.type symbol, STT_FUNC'
    662   static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
    663 }
    664 
    665 void MipsTargetELFStreamer::emitDirectiveAbiCalls() {
    666   MCAssembler &MCA = getStreamer().getAssembler();
    667   unsigned Flags = MCA.getELFHeaderEFlags();
    668   Flags |= ELF::EF_MIPS_CPIC | ELF::EF_MIPS_PIC;
    669   MCA.setELFHeaderEFlags(Flags);
    670 }
    671 
    672 void MipsTargetELFStreamer::emitDirectiveNaN2008() {
    673   MCAssembler &MCA = getStreamer().getAssembler();
    674   unsigned Flags = MCA.getELFHeaderEFlags();
    675   Flags |= ELF::EF_MIPS_NAN2008;
    676   MCA.setELFHeaderEFlags(Flags);
    677 }
    678 
    679 void MipsTargetELFStreamer::emitDirectiveNaNLegacy() {
    680   MCAssembler &MCA = getStreamer().getAssembler();
    681   unsigned Flags = MCA.getELFHeaderEFlags();
    682   Flags &= ~ELF::EF_MIPS_NAN2008;
    683   MCA.setELFHeaderEFlags(Flags);
    684 }
    685 
    686 void MipsTargetELFStreamer::emitDirectiveOptionPic0() {
    687   MCAssembler &MCA = getStreamer().getAssembler();
    688   unsigned Flags = MCA.getELFHeaderEFlags();
    689   // This option overrides other PIC options like -KPIC.
    690   Pic = false;
    691   Flags &= ~ELF::EF_MIPS_PIC;
    692   MCA.setELFHeaderEFlags(Flags);
    693 }
    694 
    695 void MipsTargetELFStreamer::emitDirectiveOptionPic2() {
    696   MCAssembler &MCA = getStreamer().getAssembler();
    697   unsigned Flags = MCA.getELFHeaderEFlags();
    698   Pic = true;
    699   // NOTE: We are following the GAS behaviour here which means the directive
    700   // 'pic2' also sets the CPIC bit in the ELF header. This is different from
    701   // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
    702   // EF_MIPS_CPIC to be mutually exclusive.
    703   Flags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
    704   MCA.setELFHeaderEFlags(Flags);
    705 }
    706 
    707 void MipsTargetELFStreamer::emitDirectiveInsn() {
    708   MipsTargetStreamer::emitDirectiveInsn();
    709   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
    710   MEF.createPendingLabelRelocs();
    711 }
    712 
    713 void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
    714                                       unsigned ReturnReg_) {
    715   MCContext &Context = getStreamer().getAssembler().getContext();
    716   const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
    717 
    718   FrameInfoSet = true;
    719   FrameReg = RegInfo->getEncodingValue(StackReg);
    720   FrameOffset = StackSize;
    721   ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
    722 }
    723 
    724 void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
    725                                      int CPUTopSavedRegOff) {
    726   GPRInfoSet = true;
    727   GPRBitMask = CPUBitmask;
    728   GPROffset = CPUTopSavedRegOff;
    729 }
    730 
    731 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
    732                                       int FPUTopSavedRegOff) {
    733   FPRInfoSet = true;
    734   FPRBitMask = FPUBitmask;
    735   FPROffset = FPUTopSavedRegOff;
    736 }
    737 
    738 void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) {
    739   // .cpload $reg
    740   // This directive expands to:
    741   // lui   $gp, %hi(_gp_disp)
    742   // addui $gp, $gp, %lo(_gp_disp)
    743   // addu  $gp, $gp, $reg
    744   // when support for position independent code is enabled.
    745   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
    746     return;
    747 
    748   // There's a GNU extension controlled by -mno-shared that allows
    749   // locally-binding symbols to be accessed using absolute addresses.
    750   // This is currently not supported. When supported -mno-shared makes
    751   // .cpload expand to:
    752   //   lui     $gp, %hi(__gnu_local_gp)
    753   //   addiu   $gp, $gp, %lo(__gnu_local_gp)
    754 
    755   StringRef SymName("_gp_disp");
    756   MCAssembler &MCA = getStreamer().getAssembler();
    757   MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
    758   MCA.registerSymbol(*GP_Disp);
    759 
    760   MCInst TmpInst;
    761   TmpInst.setOpcode(Mips::LUi);
    762   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
    763   const MCSymbolRefExpr *HiSym = MCSymbolRefExpr::create(
    764       "_gp_disp", MCSymbolRefExpr::VK_Mips_ABS_HI, MCA.getContext());
    765   TmpInst.addOperand(MCOperand::createExpr(HiSym));
    766   getStreamer().EmitInstruction(TmpInst, STI);
    767 
    768   TmpInst.clear();
    769 
    770   TmpInst.setOpcode(Mips::ADDiu);
    771   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
    772   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
    773   const MCSymbolRefExpr *LoSym = MCSymbolRefExpr::create(
    774       "_gp_disp", MCSymbolRefExpr::VK_Mips_ABS_LO, MCA.getContext());
    775   TmpInst.addOperand(MCOperand::createExpr(LoSym));
    776   getStreamer().EmitInstruction(TmpInst, STI);
    777 
    778   TmpInst.clear();
    779 
    780   TmpInst.setOpcode(Mips::ADDu);
    781   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
    782   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
    783   TmpInst.addOperand(MCOperand::createReg(RegNo));
    784   getStreamer().EmitInstruction(TmpInst, STI);
    785 
    786   forbidModuleDirective();
    787 }
    788 
    789 void MipsTargetELFStreamer::emitDirectiveCpRestore(
    790     SmallVector<MCInst, 3> &StoreInsts, int Offset) {
    791   MipsTargetStreamer::emitDirectiveCpRestore(StoreInsts, Offset);
    792   // .cprestore offset
    793   // When PIC mode is enabled and the O32 ABI is used, this directive expands
    794   // to:
    795   //    sw $gp, offset($sp)
    796   // and adds a corresponding LW after every JAL.
    797 
    798   // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
    799   // is used in non-PIC mode.
    800   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
    801     return;
    802 
    803   for (const MCInst &Inst : StoreInsts)
    804     getStreamer().EmitInstruction(Inst, STI);
    805 }
    806 
    807 void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
    808                                                  int RegOrOffset,
    809                                                  const MCSymbol &Sym,
    810                                                  bool IsReg) {
    811   // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
    812   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
    813     return;
    814 
    815   MCAssembler &MCA = getStreamer().getAssembler();
    816   MCInst Inst;
    817 
    818   // Either store the old $gp in a register or on the stack
    819   if (IsReg) {
    820     // move $save, $gpreg
    821     Inst.setOpcode(Mips::OR64);
    822     Inst.addOperand(MCOperand::createReg(RegOrOffset));
    823     Inst.addOperand(MCOperand::createReg(Mips::GP));
    824     Inst.addOperand(MCOperand::createReg(Mips::ZERO));
    825   } else {
    826     // sd $gpreg, offset($sp)
    827     Inst.setOpcode(Mips::SD);
    828     Inst.addOperand(MCOperand::createReg(Mips::GP));
    829     Inst.addOperand(MCOperand::createReg(Mips::SP));
    830     Inst.addOperand(MCOperand::createImm(RegOrOffset));
    831   }
    832   getStreamer().EmitInstruction(Inst, STI);
    833   Inst.clear();
    834 
    835   const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::create(
    836       &Sym, MCSymbolRefExpr::VK_Mips_GPOFF_HI, MCA.getContext());
    837   const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::create(
    838       &Sym, MCSymbolRefExpr::VK_Mips_GPOFF_LO, MCA.getContext());
    839 
    840   // lui $gp, %hi(%neg(%gp_rel(funcSym)))
    841   Inst.setOpcode(Mips::LUi);
    842   Inst.addOperand(MCOperand::createReg(Mips::GP));
    843   Inst.addOperand(MCOperand::createExpr(HiExpr));
    844   getStreamer().EmitInstruction(Inst, STI);
    845   Inst.clear();
    846 
    847   // addiu  $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
    848   Inst.setOpcode(Mips::ADDiu);
    849   Inst.addOperand(MCOperand::createReg(Mips::GP));
    850   Inst.addOperand(MCOperand::createReg(Mips::GP));
    851   Inst.addOperand(MCOperand::createExpr(LoExpr));
    852   getStreamer().EmitInstruction(Inst, STI);
    853   Inst.clear();
    854 
    855   // daddu  $gp, $gp, $funcreg
    856   Inst.setOpcode(Mips::DADDu);
    857   Inst.addOperand(MCOperand::createReg(Mips::GP));
    858   Inst.addOperand(MCOperand::createReg(Mips::GP));
    859   Inst.addOperand(MCOperand::createReg(RegNo));
    860   getStreamer().EmitInstruction(Inst, STI);
    861 
    862   forbidModuleDirective();
    863 }
    864 
    865 void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
    866                                                   bool SaveLocationIsRegister) {
    867   // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
    868   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
    869     return;
    870 
    871   MCInst Inst;
    872   // Either restore the old $gp from a register or on the stack
    873   if (SaveLocationIsRegister) {
    874     Inst.setOpcode(Mips::OR);
    875     Inst.addOperand(MCOperand::createReg(Mips::GP));
    876     Inst.addOperand(MCOperand::createReg(SaveLocation));
    877     Inst.addOperand(MCOperand::createReg(Mips::ZERO));
    878   } else {
    879     Inst.setOpcode(Mips::LD);
    880     Inst.addOperand(MCOperand::createReg(Mips::GP));
    881     Inst.addOperand(MCOperand::createReg(Mips::SP));
    882     Inst.addOperand(MCOperand::createImm(SaveLocation));
    883   }
    884   getStreamer().EmitInstruction(Inst, STI);
    885 
    886   forbidModuleDirective();
    887 }
    888 
    889 void MipsTargetELFStreamer::emitMipsAbiFlags() {
    890   MCAssembler &MCA = getStreamer().getAssembler();
    891   MCContext &Context = MCA.getContext();
    892   MCStreamer &OS = getStreamer();
    893   MCSectionELF *Sec = Context.getELFSection(
    894       ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
    895   MCA.registerSection(*Sec);
    896   Sec->setAlignment(8);
    897   OS.SwitchSection(Sec);
    898 
    899   OS << ABIFlagsSection;
    900 }
    901