| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 1 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
10 // This class prints an AArch64 MCInst to a .s file.
57 if (Opcode == AArch64::SYSxt)
64 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
65 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
71 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
72 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri)
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -------*- C++ -*-===//
26 #define DEBUG_TYPE "aarch64-disassembler"
256 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
257 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64LoadStoreOptimizer.cpp | 1 //=- AArch64LoadStoreOptimizer.cpp - AArch64 load/store opt. pass -*- C++ -*-=//
34 #define DEBUG_TYPE "aarch64-ldst-opt"
47 static cl::opt<unsigned> ScanLimit("aarch64-load-store-scan-limit",
54 #define AARCH64_LOAD_STORE_OPT_NAME "AArch64 load / store optimization pass"
146 INITIALIZE_PASS(AArch64LoadStoreOpt, "aarch64-ldst-opt",
153 case AArch64::STURSi:
154 case AArch64::STURDi:
155 case AArch64::STURQi:
156 case AArch64::STURBBi:
157 case AArch64::STURHHi
[all...] |
| AArch64CallingConvention.h | 10 // This file contains the custom routines for the AArch64 Calling Convention
18 #include "AArch64.h"
28 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
29 AArch64::X3, AArch64::X4, AArch64::X5,
30 AArch64::X6, AArch64::X7}
[all...] |
| AArch64PBQPRegAlloc.cpp | 1 //===-- AArch64PBQPRegAlloc.cpp - AArch64 specific PBQP constraints -------===//
9 // This file contains the AArch64 / Cortex-A57 specific register allocation
18 #define DEBUG_TYPE "aarch64-pbqp"
20 #include "AArch64.h"
38 return AArch64::FPR32RegClass.contains(reg) ||
39 AArch64::FPR64RegClass.contains(reg) ||
40 AArch64::FPR128RegClass.contains(reg);
48 case AArch64::S1:
49 case AArch64::S3:
50 case AArch64::S5
[all...] |
| AArch64InstrInfo.cpp | 1 //===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===//
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
32 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP),
42 if (MI->getOpcode() == AArch64::INLINEASM)
66 case AArch64::Bcc:
70 case AArch64::CBZW:
71 case AArch64::CBZX:
72 case AArch64::CBNZW:
73 case AArch64::CBNZX
[all...] |
| AArch64RegisterInfo.cpp | 1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
10 // This file contains the AArch64 implementation of the TargetRegisterInfo
39 : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {}
109 Reserved.set(AArch64::SP);
110 Reserved.set(AArch64::XZR);
111 Reserved.set(AArch64::WSP);
112 Reserved.set(AArch64::WZR);
115 Reserved.set(AArch64::FP);
116 Reserved.set(AArch64::W29);
120 Reserved.set(AArch64::X18); // Platform registe
[all...] |
| AArch64BranchRelaxation.cpp | 1 //===-- AArch64BranchRelaxation.cpp - AArch64 branch relaxation -----------===//
12 #include "AArch64.h"
27 #define DEBUG_TYPE "aarch64-branch-relax"
30 BranchRelaxation("aarch64-branch-relax", cl::Hidden, cl::init(true),
34 TBZDisplacementBits("aarch64-tbz-offset-bits", cl::Hidden, cl::init(14),
38 CBZDisplacementBits("aarch64-cbz-offset-bits", cl::Hidden, cl::init(19),
42 BCCDisplacementBits("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19),
52 #define AARCH64_BR_RELAX_NAME "AArch64 branch relaxation pass"
115 INITIALIZE_PASS(AArch64BranchRelaxation, "aarch64-branch-relax",
239 BuildMI(OrigBB, DebugLoc(), TII->get(AArch64::B)).addMBB(NewBB)
[all...] |
| AArch64ConditionalCompares.cpp | 1 //===-- AArch64ConditionalCompares.cpp --- CCMP formation for AArch64 -----===//
20 #include "AArch64.h"
45 #define DEBUG_TYPE "aarch64-ccmp"
50 "aarch64-ccmp-limit", cl::init(30), cl::Hidden,
54 static cl::opt<bool> Stress("aarch64-stress-ccmp", cl::Hidden,
101 // instructions. The AArch64 conditional compare instructions have an immediate
260 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR)
285 case AArch64::CBZW:
286 case AArch64::CBZX
[all...] |
| AArch64ISelDAGToDAG.cpp | 1 //===-- AArch64ISelDAGToDAG.cpp - A dag to dag inst selector for AArch64 --===//
10 // This file defines an instruction selector for the AArch64 target.
28 #define DEBUG_TYPE "aarch64-isel"
31 /// AArch64DAGToDAGISel - AArch64 specific code to select AArch64 machine
51 return "AArch64 Instruction Selection";
237 // Require the address to be in a register. That is safe for all AArch64
452 /// SelectMLAV64LaneV128 - AArch64 supports vector MLAs where one multiplicand
483 MLAOpc = AArch64::MLAv4i16_indexed;
486 MLAOpc = AArch64::MLAv8i16_indexed
[all...] |
| AArch64ExpandPseudoInsts.cpp | 29 #define AARCH64_EXPAND_PSEUDO_NAME "AArch64 pseudo instruction expansion pass"
56 INITIALIZE_PASS(AArch64ExpandPseudo, "aarch64-expand-pseudo",
110 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
112 .addReg(AArch64::XZR)
120 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
177 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
179 .addReg(AArch64::XZR)
197 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
222 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
360 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri)
[all...] |
| AArch64FastISel.cpp | 1 //===-- AArch6464FastISel.cpp - AArch64 FastISel implementation -----------===//
10 // This file defines the AArch64-specific support for the FastISel class. Some
16 #include "AArch64.h"
324 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
325 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
344 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass
345 : &AArch64::GPR32RegClass;
346 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
370 unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi
[all...] |
| AArch64AdvSIMDScalarPass.cpp | 36 #include "AArch64.h"
51 #define DEBUG_TYPE "aarch64-simd-scalar"
56 TransformAll("aarch64-simd-scalar-force-all",
109 INITIALIZE_PASS(AArch64AdvSIMDScalar, "aarch64-simd-scalar",
117 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);
118 return AArch64::GPR64RegClass.contains(Reg);
124 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) &&
126 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&
127 SubReg == AArch64::dsub);
129 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) |
[all...] |
| AArch64A53Fix835769.cpp | 18 #include "AArch64.h"
32 #define DEBUG_TYPE "aarch64-fix-cortex-a53-835769"
44 case AArch64::PRFMl:
45 case AArch64::PRFMroW:
46 case AArch64::PRFMroX:
47 case AArch64::PRFMui:
48 case AArch64::PRFUMi:
63 case AArch64::MSUBXrrr:
64 case AArch64::MADDXrrr:
65 case AArch64::SMADDLrrr
[all...] |
| AArch64ConditionOptimizer.cpp | 1 //=- AArch64ConditionOptimizer.cpp - Remove useless comparisons for AArch64 -=//
61 #include "AArch64.h"
83 #define DEBUG_TYPE "aarch64-condopt"
108 return "AArch64 Condition Optimizer";
119 INITIALIZE_PASS_BEGIN(AArch64ConditionOptimizer, "aarch64-condopt",
120 "AArch64 CondOpt Pass", false, false)
122 INITIALIZE_PASS_END(AArch64ConditionOptimizer, "aarch64-condopt",
123 "AArch64 CondOpt Pass", false, false)
144 if (I->getOpcode() != AArch64::Bcc)
153 case AArch64::SUBSWri
[all...] |
| AArch64FrameLowering.cpp | 1 //===- AArch64FrameLowering.cpp - AArch64 Frame Lowering -------*- C++ -*-====//
10 // This file contains the AArch64 implementation of TargetFrameLowering class.
12 // On AArch64, stack frames are structured as follows:
112 static cl::opt<bool> EnableRedZone("aarch64-redzone",
113 cl::desc("enable use of redzone on AArch64"),
192 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, Amount, TII);
198 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, -CalleePopAmount,
239 if (HasFP && (FramePtr == Reg || Reg == AArch64::LR))
[all...] |
| AArch64AsmPrinter.cpp | 1 //===-- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer --------------===//
11 // of machine-dependent LLVM code to the AArch64 assembly language.
16 #include "AArch64.h"
59 return "AArch64 Assembly Printer";
247 RegToPrint, isVector ? AArch64::vreg : AArch64::NoRegAltName);
273 unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR;
288 RC = &AArch64::FPR8RegClass;
291 RC = &AArch64::FPR16RegClass
[all...] |
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
11 // the AArch64 target useful for the compiler back-end and the MC libraries.
22 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
32 case AArch64::X0: return AArch64::W0;
33 case AArch64::X1: return AArch64::W1;
34 case AArch64::X2: return AArch64::W2;
35 case AArch64::X3: return AArch64::W3
[all...] |
| AArch64BaseInfo.cpp | 1 //===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
10 // This file provides basic encoding and assembly information for AArch64.
148 {"pan", PAN, {AArch64::HasV8_1aOps}},
151 {"uao", UAO, {AArch64::HasV8_2aOps}},
159 {"csync", CSync, {AArch64::FeatureSPE}},
206 {"id_aa64mmfr2_el1", ID_A64MMFR2_EL1, {AArch64::HasV8_2aOps}},
266 {"lorid_el1", LORID_EL1, {AArch64::HasV8_1aOps}},
777 {"cpm_ioacc_ctl_el3", CPM_IOACC_CTL_EL3, {AArch64::ProcCyclone}},
780 {"pan", PAN, {AArch64::HasV8_1aOps}},
783 {"lorsa_el1", LORSA_EL1, {AArch64::HasV8_1aOps}}
[all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AsmBackend.cpp | 1 //===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===//
10 #include "AArch64.h"
36 return AArch64::NumTargetFixupKinds;
40 const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
93 case AArch64::fixup_aarch64_tlsdesc_call:
100 case AArch64::fixup_aarch64_movw:
103 case AArch64::fixup_aarch64_pcrel_branch14:
104 case AArch64::fixup_aarch64_add_imm12:
105 case AArch64::fixup_aarch64_ldst_imm12_scale1:
106 case AArch64::fixup_aarch64_ldst_imm12_scale2
[all...] |
| AArch64FixupKinds.h | 1 //===-- AArch64FixupKinds.h - AArch64 Specific Fixup Entries ----*- C++ -*-===//
16 namespace AArch64 {
73 } // end namespace AArch64
|
| AArch64ELFObjectWriter.cpp | 1 //===-- AArch64ELFObjectWriter.cpp - AArch64 ELF Writer -------------------===//
70 case AArch64::fixup_aarch64_pcrel_adr_imm21:
73 case AArch64::fixup_aarch64_pcrel_adrp_imm21:
83 case AArch64::fixup_aarch64_pcrel_branch26:
85 case AArch64::fixup_aarch64_pcrel_call26:
87 case AArch64::fixup_aarch64_ldr_pcrel_imm19:
91 case AArch64::fixup_aarch64_pcrel_branch14:
93 case AArch64::fixup_aarch64_pcrel_branch19:
106 case AArch64::fixup_aarch64_add_imm12:
126 case AArch64::fixup_aarch64_ldst_imm12_scale1
[all...] |
| /external/llvm/host/include/llvm/Config/ |
| Targets.def | 29 LLVM_TARGET(AArch64)
|
| /external/llvm/device/include/llvm/Config/ |
| Targets.def | 35 LLVM_TARGET(AArch64)
40 LLVM_TARGET(AArch64)
|
| /frameworks/compile/mclinker/ |
| Android.mk | 26 # AArch64 Code Generation Libraries
28 lib/Target/AArch64 \
29 lib/Target/AArch64/TargetInfo
|
