| /toolchain/binutils/binutils-2.25/gold/testsuite/ |
| thumb_blx_out_of_range.s | 2 # Test THUMB/THUMB-2 blx instructions just out of the branch range limits.
44 # Bit 1 of the BLX target comes from bit 1 of branch base address,
45 # which is BLX instruction's address + 4. We intentionally put this
46 # forward BLX at an address n*4 + 2 so that the branch offset is
|
| /external/llvm/test/MC/ARM/ |
| thumb-not-mclass.s | 12 @ BLX (immediate)
14 blx _baz
|
| basic-thumb-instructions.s | 151 @ BL/BLX
153 blx #884800
154 blx #1769600
156 @ CHECK: blx #884800 @ encoding: [0xd8,0xf0,0x20,0xe8]
157 @ CHECK: blx #1769600 @ encoding: [0xb0,0xf1,0x40,0xe8]
178 @ BL/BLX (immediate)
181 blx _baz
187 @ CHECK: blx _baz @ encoding: [A,0xf0'A',A,0xc0'A']
189 @ CHECK-BE: blx _baz @ encoding: [0xf0'A',A,0xc0'A',A]
194 @ BLX (register
[all...] |
| basic-arm-instructions.s | 603 @ BL/BLX (immediate)
608 blx _bar
610 blx #32424576
611 blx #16212288
621 @ CHECK: blx _bar @ encoding: [A,A,A,0xfa]
623 @ CHECK-BE: blx _bar @ encoding: [0xfa,A,A,A]
626 @ CHECK: blx #32424576 @ encoding: [0xa0,0xb0,0x7b,0xfa]
627 @ CHECK: blx #16212288 @ encoding: [0x50,0xd8,0x3d,0xfa]
629 @ BLX (register)
631 blx r
[all...] |
| v8_IT_manual.s | 309 @ BLX, encoding T1
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| blx-bad.d | 2 #name: BLX encoding
15 4: f7ff effc blx 0 <ARM>
17 a: f7ff effa blx 0 <ARM>
19 10: f7ff eff6 blx 0 <ARM>
23 1e: f7ff eff0 blx 0 <ARM>
|
| blx-local.d | 1 #name: Local BLX instructions
5 # stderr: blx-local.l
6 # Test assembler resolution of blx and bl instructions in ARM mode.
10 0+00 <[^>]*> fa000006 blx 00000020 <foo>
12 0+08 <[^>]*> fa000004 blx 00000020 <foo>
14 0+10 <[^>]*> fa00000b blx 00000044 <fooundefarm>
16 0+18 <[^>]*> fa000001 blx 00000024 <fooundefthumb>
|
| armv8-a-it-bad.l | 10 .*:52: Warning: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Hi-register ADD, MOV, CMP, BX, BLX using pc
|
| thumb2_bad_reg.s | 92 @ BLX (register)
93 blx r13 @ OK
94 blx r15
|
| /external/pcre/dist/sljit/ |
| sljitNativeARM_T2_32.c | 108 #define BLX 0x4780
[all...] |
| sljitNativeARM_32.c | 83 #define BLX 0xe12fff30
263 return push_inst(compiler, BLX | RM(TMP_REG1));
486 inst[1] = BLX | RM(TMP_REG1);
[all...] |
| /external/v8/src/arm/ |
| constants-arm.h | 165 BLX = 3 << 4,
|
| assembler-arm.cc | 444 B24 | B21 | 15 * B16 | 15 * B12 | 15 * B8 | BLX;
757 // blx ip
816 DCHECK_EQ(5 * B25, instr & 7 * B25); // b, bl, or blx imm24
820 // blx uses bit 24 to encode bit 2 of imm26
902 DCHECK_EQ(5 * B25, instr & 7 * B25); // b, bl, or blx imm24
904 // blx uses bit 24 to encode bit 2 of imm26
931 DCHECK((instr & 7*B25) == 5*B25); // b, bl, or blx
936 b = "blx";
1390 void Assembler::blx(int branch_offset) { \/\/ v5 and above function in class:v8::internal::Assembler
1399 void Assembler::blx(Register target, Condition cond) { \/\/ v5 and above function in class:v8::internal::Assembler
1423 void Assembler::blx(Label* L) { function in class:v8::internal::Assembler
[all...] |
| simulator-arm.cc | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
