| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 339 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE,
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 118 setOperationAction(ISD::CTTZ, MVT::i8, Expand);
119 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 318 case ISD::CTTZ: return "cttz";
|
| LegalizeVectorOps.cpp | 286 case ISD::CTTZ:
[all...] |
| LegalizeVectorTypes.cpp | 75 case ISD::CTTZ:
628 case ISD::CTTZ:
[all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 66 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
393 if (N->getOpcode() == ISD::CTTZ) {
[all...] |
| SelectionDAG.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 138 setOperationAction(ISD::CTTZ, MVT::i64, Custom);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 157 setOperationAction(ISD::CTTZ, VT, Expand);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 585 // NEON does not have single instruction CTTZ for vectors.
586 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
587 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
588 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
589 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
591 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
592 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
593 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
594 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 263 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
264 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
265 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 335 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
336 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
345 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
346 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
348 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
726 setOperationAction(ISD::CTTZ, VT, Expand);
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 254 setOperationAction(ISD::CTTZ, VT, Expand);
329 setOperationAction(ISD::CTTZ, VT, Expand);
474 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 342 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
343 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 186 setOperationAction(ISD::CTTZ, VT, Expand);
311 setOperationAction(ISD::CTTZ, VT, Legal);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 207 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
213 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
483 setOperationAction(ISD::CTTZ, VT, Expand);
[all...] |
