| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 65 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false,
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false,
81 MO.push_back(MachineOperand::CreateReg(0, false, false,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCTOCRegDeps.cpp | 122 MI.addOperand(MachineOperand::CreateReg(PPC::X2,
|
| PPCInstrInfo.cpp | 501 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
512 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
570 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
584 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUMCInstLower.cpp | 51 MCOp = MCOperand::CreateReg(MO.getReg());
|
| R600InstrInfo.cpp | 218 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
242 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegStackify.cpp | 69 MI->addOperand(MachineOperand::CreateReg(WebAssembly::EXPR_STACK,
82 MI->addOperand(MachineOperand::CreateReg(WebAssembly::EXPR_STACK,
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 115 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0,
159 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0,
199 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0,
235 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0,
|
| HexagonPeephole.cpp | 223 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
230 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc.first,
|
| HexagonHardwareLoops.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2ITBlockPass.cpp | 200 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
229 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
|
| Thumb2InstrInfo.cpp | 40 NopInst.addOperand(MCOperand::createReg(0));
490 MI.addOperand(MachineOperand::CreateReg(0, false));
521 MI.addOperand(MachineOperand::CreateReg(0, false));
|
| /external/llvm/include/llvm/CodeGen/ |
| FunctionLoweringInfo.h | 164 unsigned CreateReg(MVT VT);
|
| MachineInstrBuilder.h | 69 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
|
| MachineOperand.h | 597 static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
|
| /external/llvm/lib/CodeGen/ |
| LiveVariables.cpp | 247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
270 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
383 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
400 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
|
| ExpandPostRAPseudos.cpp | 76 CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
|
| MachineInstr.cpp | 636 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
640 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 596 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
644 Ops.push_back(MachineOperand::CreateReg(
758 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*IsDef=*/true));
807 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
813 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
826 Ops.push_back(MachineOperand::CreateReg(
832 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/true,
[all...] |
| FunctionLoweringInfo.cpp | 345 /// CreateReg - Allocate a single virtual register for the given type.
346 unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
371 unsigned R = CreateReg(RegisterVT);
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIShrinkInstructions.cpp | 192 return MachineOperand::CreateReg(Orig.getReg(),
|
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 283 Inst.addOperand(MCOperand::createReg(getReg()));
305 Inst.addOperand(MCOperand::createReg(getMemBase()));
308 Inst.addOperand(MCOperand::createReg(getMemOffsetReg()));
314 Inst.addOperand(MCOperand::createReg(getMemBase()));
329 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind,
466 MCOperand PrevReg = MCOperand::createReg(Sparc::G0);
743 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E));
804 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | [all...] |
| X86Operand.h | 386 Inst.addOperand(MCOperand::createReg(getReg()));
417 Inst.addOperand(MCOperand::createReg(RegNo));
430 Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
432 Inst.addOperand(MCOperand::createReg(getMemIndexReg()));
434 Inst.addOperand(MCOperand::createReg(getMemSegReg()));
448 Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
449 Inst.addOperand(MCOperand::createReg(getMemSegReg()));
453 Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
463 Inst.addOperand(MCOperand::createReg(getMemSegReg()));
475 CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc
[all...] |
| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | 354 Inst.addOperand(MCOperand::createReg(getReg()));
582 static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc S,
[all...] |
