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      1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains code to lower AMDGPU MachineInstrs to their corresponding
     11 // MCInst.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 //
     15 
     16 #include "AMDGPUMCInstLower.h"
     17 #include "AMDGPUAsmPrinter.h"
     18 #include "R600InstrInfo.h"
     19 #include "llvm/CodeGen/MachineBasicBlock.h"
     20 #include "llvm/CodeGen/MachineInstr.h"
     21 #include "llvm/Constants.h"
     22 #include "llvm/MC/MCInst.h"
     23 #include "llvm/MC/MCStreamer.h"
     24 #include "llvm/Support/ErrorHandling.h"
     25 
     26 using namespace llvm;
     27 
     28 AMDGPUMCInstLower::AMDGPUMCInstLower() { }
     29 
     30 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
     31   OutMI.setOpcode(MI->getOpcode());
     32 
     33   for (unsigned i = 0, e = MI->getNumExplicitOperands(); i != e; ++i) {
     34     const MachineOperand &MO = MI->getOperand(i);
     35 
     36     MCOperand MCOp;
     37     switch (MO.getType()) {
     38     default:
     39       llvm_unreachable("unknown operand type");
     40     case MachineOperand::MO_FPImmediate: {
     41       const APFloat &FloatValue = MO.getFPImm()->getValueAPF();
     42       assert(&FloatValue.getSemantics() == &APFloat::IEEEsingle &&
     43              "Only floating point immediates are supported at the moment.");
     44       MCOp = MCOperand::CreateFPImm(FloatValue.convertToFloat());
     45       break;
     46     }
     47     case MachineOperand::MO_Immediate:
     48       MCOp = MCOperand::CreateImm(MO.getImm());
     49       break;
     50     case MachineOperand::MO_Register:
     51       MCOp = MCOperand::CreateReg(MO.getReg());
     52       break;
     53     }
     54     OutMI.addOperand(MCOp);
     55   }
     56 }
     57 
     58 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
     59   AMDGPUMCInstLower MCInstLowering;
     60 
     61   // Ignore placeholder instructions:
     62   if (MI->getOpcode() == AMDGPU::MASK_WRITE) {
     63     return;
     64   }
     65 
     66   if (MI->isBundle()) {
     67     const MachineBasicBlock *MBB = MI->getParent();
     68     MachineBasicBlock::const_instr_iterator I = MI;
     69     ++I;
     70     while (I != MBB->end() && I->isInsideBundle()) {
     71       MCInst MCBundleInst;
     72       const MachineInstr *BundledInst = I;
     73       MCInstLowering.lower(BundledInst, MCBundleInst);
     74       OutStreamer.EmitInstruction(MCBundleInst);
     75       ++I;
     76     }
     77   } else {
     78     MCInst TmpInst;
     79     MCInstLowering.lower(MI, TmpInst);
     80     OutStreamer.EmitInstruction(TmpInst);
     81   }
     82 }
     83