| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 512 /// FLOG, FLOG2, FLOG10, FEXP, FEXP2,
516 FLOG, FLOG2, FLOG10, FEXP, FEXP2,
[all...] |
| BasicTTIImpl.h | 639 ISD = ISD::FLOG2;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 171 case ISD::FLOG2: return "flog2";
|
| LegalizeVectorOps.cpp | 313 case ISD::FLOG2:
[all...] |
| LegalizeFloatTypes.cpp | 88 case ISD::FLOG2: R = SoftenFloatRes_FLOG2(N); break;
[all...] |
| LegalizeVectorTypes.cpp | 85 case ISD::FLOG2:
640 case ISD::FLOG2:
[all...] |
| LegalizeDAG.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 87 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
349 setOperationAction(ISD::FLOG2, VT, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 314 setOperationAction(ISD::FLOG2, Ty, Legal);
[all...] |
| MipsISelLowering.cpp | 369 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 301 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
352 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
386 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
653 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 507 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
525 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
542 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
666 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 458 setOperationAction(ISD::FLOG2, VT, Expand);
700 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 674 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
[all...] |
