| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 518 /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
523 FMINNUM, FMAXNUM,
524 /// FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that
[all...] |
| BasicTTIImpl.h | 648 ISD = ISD::FMAXNUM;
|
| SelectionDAG.h | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 789 setOperationAction(ISD::FMAXNUM, VT, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 154 case ISD::FMAXNUM: return "fmaxnum";
|
| LegalizeVectorOps.cpp | 303 case ISD::FMAXNUM:
[all...] |
| LegalizeFloatTypes.cpp | 78 case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break;
[all...] |
| SelectionDAGBuilder.cpp | [all...] |
| LegalizeVectorTypes.cpp | 111 case ISD::FMAXNUM:
671 case ISD::FMAXNUM:
[all...] |
| LegalizeDAG.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 84 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
257 setTargetDAGCombine(ISD::FMAXNUM);
[all...] |
| AMDGPUISelLowering.cpp | 93 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
343 setOperationAction(ISD::FMAXNUM, VT, Expand);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 306 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
398 setOperationAction(ISD::FMAXNUM, Ty, Legal);
703 ISD::FMINNUM, ISD::FMAXNUM})
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 706 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 679 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
[all...] |
