| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 518 /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
522 /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.
523 FMINNUM, FMAXNUM,
524 /// FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that
[all...] |
| BasicTTIImpl.h | 645 ISD = ISD::FMINNUM;
|
| SelectionDAG.h | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 788 setOperationAction(ISD::FMINNUM, VT, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 153 case ISD::FMINNUM: return "fminnum";
|
| LegalizeVectorOps.cpp | 302 case ISD::FMINNUM:
[all...] |
| LegalizeFloatTypes.cpp | 77 case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break;
[all...] |
| SelectionDAGBuilder.cpp | [all...] |
| LegalizeVectorTypes.cpp | 110 case ISD::FMINNUM:
670 case ISD::FMINNUM:
[all...] |
| LegalizeDAG.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 83 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
256 setTargetDAGCombine(ISD::FMINNUM);
[all...] |
| AMDGPUISelLowering.cpp | 92 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
342 setOperationAction(ISD::FMINNUM, VT, Expand);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 305 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
397 setOperationAction(ISD::FMINNUM, Ty, Legal);
703 ISD::FMINNUM, ISD::FMAXNUM})
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 705 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 678 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
[all...] |
