1 /****************************************************************************** 2 * 3 * Copyright (C) 2015 The Android Open Source Project 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ***************************************************************************** 18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore 19 */ 20 21 /*! 22 ************************************************************************** 23 * \file ih264d_thread_compute_bs.c 24 * 25 * \brief 26 * Contains routines that for multi-thread decoder 27 * 28 * Detailed_description 29 * 30 * \date 31 * 20/02/2012 32 * 33 * \author ZR 34 ************************************************************************** 35 */ 36 #include "ih264d_error_handler.h" 37 #include "ih264d_debug.h" 38 #include <string.h> 39 #include "ih264d_defs.h" 40 #include "ih264d_debug.h" 41 #include "ih264d_tables.h" 42 #include "ih264d_structs.h" 43 #include "ih264d_defs.h" 44 #include "ih264d_mb_utils.h" 45 46 #include "ih264d_thread_compute_bs.h" 47 #include "ithread.h" 48 #include "ih264d_deblocking.h" 49 #include "ih264d_process_pslice.h" 50 #include "ih264d_process_intra_mb.h" 51 #include "ih264d_mb_utils.h" 52 #include "ih264d_tables.h" 53 #include "ih264d_format_conv.h" 54 #include "ih264d_defs.h" 55 UWORD16 ih264d_update_csbp_8x8(UWORD16 u2_luma_csbp); 56 void ih264d_fill_bs2_horz_vert(UWORD32 *pu4_bs, /* Base pointer of BS table */ 57 WORD32 u4_left_mb_csbp, /* csbp of left mb */ 58 WORD32 u4_top_mb_csbp, /* csbp of top mb */ 59 WORD32 u4_cur_mb_csbp, /* csbp of current mb */ 60 const UWORD32 *pu4_packed_bs2, const UWORD16 *pu2_4x4_v2h_reorder); 61 void ih264d_copy_intra_pred_line(dec_struct_t *ps_dec, 62 dec_mb_info_t *ps_cur_mb_info, 63 UWORD32 nmb_index); 64 65 #define BS_MB_GROUP 4 66 #define DEBLK_MB_GROUP 1 67 #define FORMAT_CONV_MB_GROUP 4 68 69 /*****************************************************************************/ 70 /* */ 71 /* Function Name : ih264d_compute_bs_non_mbaff_thread */ 72 /* */ 73 /* Description : This function computes the pointers of left,top & current*/ 74 /* : Nnz, MvPred & deblk_mb_t and supplies to FillBs function for*/ 75 /* : Boundary Strength Calculation .this function is used */ 76 /* : BS being calculated in separate thread */ 77 /* Inputs : pointer to decoder context,cur_mb_info,u4_mb_num */ 78 /* Processing : */ 79 /* */ 80 /* Outputs : Produces the Boundary Strength for Current Mb */ 81 /* Returns : None */ 82 /* */ 83 /* Revision History: */ 84 /* */ 85 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 86 /* ITTIAM */ 87 /*****************************************************************************/ 88 89 void ih264d_compute_bs_non_mbaff_thread(dec_struct_t * ps_dec, 90 dec_mb_info_t * ps_cur_mb_info, 91 UWORD32 u4_mb_num) 92 { 93 /* Mvpred and Nnz for top and Courrent */ 94 mv_pred_t *ps_cur_mv_pred, *ps_top_mv_pred = NULL, *ps_left_mv_pred; 95 /* deblk_mb_t Params */ 96 deblk_mb_t *ps_cur_mb_params; /*< Parameters of current MacroBlock */ 97 deblkmb_neighbour_t *ps_deblk_top_mb; 98 99 /* Reference Index to POC mapping*/ 100 void ** apv_map_ref_idx_to_poc; 101 UWORD32 u4_leftmbtype; 102 103 UWORD16 u2_left_csbp, u2_top_csbp, u2_cur_csbp; 104 105 /* Set of flags */ 106 UWORD32 u4_cur_mb_intra, u1_top_mb_typ, u4_cur_mb_fld; 107 UWORD32 u1_cur_mb_type; 108 UWORD32 * pu4_bs_table; 109 110 /* Neighbour availability */ 111 /* Initialization */ 112 const UWORD32 u2_mbx = ps_cur_mb_info->u2_mbx; 113 const UWORD32 u2_mby = ps_cur_mb_info->u2_mby; 114 const UWORD32 u1_pingpong = u2_mbx & 0x01; 115 116 PROFILE_DISABLE_BOUNDARY_STRENGTH() 117 ps_deblk_top_mb = ps_dec->ps_deblk_top_mb + u2_mbx; 118 119 /* Pointer assignment for Current DeblkMB, Current Mv Pred */ 120 ps_cur_mb_params = ps_dec->ps_deblk_pic + u4_mb_num; 121 ps_cur_mv_pred = ps_dec->s_cur_pic.ps_mv + (u4_mb_num << 4); 122 123 apv_map_ref_idx_to_poc = 124 (void **)ps_dec->ps_computebs_cur_slice->ppv_map_ref_idx_to_poc 125 + 1; 126 u1_cur_mb_type = ps_cur_mb_params->u1_mb_type; 127 u1_top_mb_typ = ps_deblk_top_mb->u1_mb_type; 128 ps_deblk_top_mb->u1_mb_type = u1_cur_mb_type; 129 130 { 131 ps_cur_mb_params->u1_topmb_qp = ps_deblk_top_mb->u1_mb_qp; 132 ps_deblk_top_mb->u1_mb_qp = ps_cur_mb_params->u1_mb_qp; 133 134 ps_cur_mb_params->u1_left_mb_qp = ps_dec->deblk_left_mb[1].u1_mb_qp; 135 ps_dec->deblk_left_mb[1].u1_mb_qp = ps_cur_mb_params->u1_mb_qp; 136 137 } 138 139 /* if no deblocking required for current Mb then continue */ 140 /* Check next Mbs in Mb group */ 141 if(ps_cur_mb_params->u1_deblocking_mode & MB_DISABLE_FILTERING) 142 { 143 void ** pu4_map_ref_idx_to_poc_l1 = apv_map_ref_idx_to_poc + 144 POC_LIST_L0_TO_L1_DIFF; 145 { 146 /* Store Parameter for Top MvPred refernce frame Address */ 147 148 void ** ppv_top_mv_pred_addr = ps_cur_mb_info->ps_curmb->u4_pic_addrress; 149 WORD8 * p1_refTop0 = (ps_cur_mv_pred + 12)->i1_ref_frame; 150 WORD8 * p1_refTop1 = (ps_cur_mv_pred + 14)->i1_ref_frame; 151 152 /* Store Left addresses for Next Mb */ 153 void ** ppv_left_mv_pred_addr = 154 ps_dec->ps_left_mvpred_addr[!u1_pingpong][1].u4_add; 155 WORD8 * p1_refleft0 = (ps_cur_mv_pred + 3)->i1_ref_frame; 156 157 158 ppv_top_mv_pred_addr[0] = apv_map_ref_idx_to_poc[p1_refTop0[0]]; 159 ppv_top_mv_pred_addr[1] = pu4_map_ref_idx_to_poc_l1[p1_refTop0[1]]; 160 161 ppv_left_mv_pred_addr[2] = apv_map_ref_idx_to_poc[p1_refTop1[0]]; 162 ppv_top_mv_pred_addr[2] = apv_map_ref_idx_to_poc[p1_refTop1[0]]; 163 ppv_left_mv_pred_addr[3] = pu4_map_ref_idx_to_poc_l1[p1_refTop1[1]]; 164 ppv_top_mv_pred_addr[3] = pu4_map_ref_idx_to_poc_l1[p1_refTop1[1]]; 165 166 ppv_left_mv_pred_addr[0] = apv_map_ref_idx_to_poc[p1_refleft0[0]]; 167 ppv_left_mv_pred_addr[1] = pu4_map_ref_idx_to_poc_l1[p1_refleft0[1]]; 168 //} 169 /* Storing the leftMbtype for next Mb */ 170 ps_dec->deblk_left_mb[1].u1_mb_type = ps_cur_mb_params->u1_mb_type; 171 } 172 173 return; 174 } 175 176 /* Flag for extra left Edge */ 177 ps_cur_mb_params->u1_single_call = 1; 178 179 /* Update the Left deblk_mb_t and Left MvPred Parameters */ 180 if(!u2_mbx) 181 { 182 u4_leftmbtype = 0; 183 184 /* Initialize the ps_left_mv_pred with Junk but Valid Location */ 185 /* to avoid invalid memory access */ 186 /* this is read only pointer */ 187 ps_left_mv_pred = ps_cur_mv_pred + 3; 188 } 189 else 190 { 191 u4_leftmbtype = ps_dec->deblk_left_mb[1].u1_mb_type; 192 193 /* Come to Left Most Edge of the MB */ 194 ps_left_mv_pred = ps_cur_mv_pred - (1 << 4) + 3; 195 } 196 197 if(!u2_mby) 198 u1_top_mb_typ = 0; 199 200 /* MvPred Pointer Calculation */ 201 /* CHANGED CODE */ 202 ps_top_mv_pred = ps_cur_mv_pred - (ps_dec->u2_frm_wd_in_mbs << 4) + 12; 203 204 u4_cur_mb_intra = u1_cur_mb_type & D_INTRA_MB; 205 u4_cur_mb_fld = !!(u1_cur_mb_type & D_FLD_MB); 206 /* Compute BS function */ 207 pu4_bs_table = ps_cur_mb_params->u4_bs_table; 208 209 u2_cur_csbp = ps_cur_mb_info->ps_curmb->u2_luma_csbp; 210 u2_left_csbp = ps_cur_mb_info->ps_left_mb->u2_luma_csbp; 211 u2_top_csbp = ps_cur_mb_info->ps_top_mb->u2_luma_csbp; 212 213 /* Compute BS function */ 214 if(ps_dec->ps_cur_sps->u1_profile_idc == HIGH_PROFILE_IDC) 215 { 216 if(ps_cur_mb_info->u1_tran_form8x8 == 1) 217 { 218 u2_cur_csbp = ih264d_update_csbp_8x8( 219 ps_cur_mb_info->ps_curmb->u2_luma_csbp); 220 } 221 222 if(ps_cur_mb_info->ps_left_mb->u1_tran_form8x8 == 1) 223 { 224 u2_left_csbp = ih264d_update_csbp_8x8( 225 ps_cur_mb_info->ps_left_mb->u2_luma_csbp); 226 } 227 228 if(ps_cur_mb_info->ps_top_mb->u1_tran_form8x8 == 1) 229 { 230 u2_top_csbp = ih264d_update_csbp_8x8( 231 ps_cur_mb_info->ps_top_mb->u2_luma_csbp); 232 } 233 } 234 if(u4_cur_mb_intra) 235 { 236 237 pu4_bs_table[4] = 0x04040404; 238 pu4_bs_table[0] = u4_cur_mb_fld ? 0x03030303 : 0x04040404; 239 pu4_bs_table[1] = 0x03030303; 240 pu4_bs_table[2] = 0x03030303; 241 pu4_bs_table[3] = 0x03030303; 242 pu4_bs_table[5] = 0x03030303; 243 pu4_bs_table[6] = 0x03030303; 244 pu4_bs_table[7] = 0x03030303; 245 } 246 else 247 { 248 UWORD32 u4_is_non16x16 = !!(u1_cur_mb_type & D_PRED_NON_16x16); 249 UWORD32 u4_is_b = 250 (ps_dec->ps_computebs_cur_slice->slice_type == B_SLICE); 251 252 253 254 255 256 257 ih264d_fill_bs2_horz_vert(pu4_bs_table, u2_left_csbp, u2_top_csbp, 258 u2_cur_csbp, gau4_ih264d_packed_bs2, 259 gau2_ih264d_4x4_v2h_reorder); 260 261 if(u4_leftmbtype & D_INTRA_MB) 262 pu4_bs_table[4] = 0x04040404; 263 264 if(u1_top_mb_typ & D_INTRA_MB) 265 pu4_bs_table[0] = u4_cur_mb_fld ? 0x03030303 : 0x04040404; 266 267 ps_dec->pf_fill_bs1[u4_is_b][u4_is_non16x16]( 268 ps_cur_mv_pred, ps_top_mv_pred, apv_map_ref_idx_to_poc, 269 pu4_bs_table, ps_left_mv_pred, 270 &(ps_dec->ps_left_mvpred_addr[u1_pingpong][1]), 271 ps_cur_mb_info->ps_top_mb->u4_pic_addrress, 272 (4 >> u4_cur_mb_fld)); 273 } 274 275 { 276 void ** pu4_map_ref_idx_to_poc_l1 = apv_map_ref_idx_to_poc + 277 POC_LIST_L0_TO_L1_DIFF; 278 { 279 /* Store Parameter for Top MvPred refernce frame Address */ 280 281 void ** ppv_top_mv_pred_addr = ps_cur_mb_info->ps_curmb->u4_pic_addrress; 282 WORD8 * p1_refTop0 = (ps_cur_mv_pred + 12)->i1_ref_frame; 283 WORD8 * p1_refTop1 = (ps_cur_mv_pred + 14)->i1_ref_frame; 284 285 /* Store Left addresses for Next Mb */ 286 void ** ppv_left_mv_pred_addr = 287 ps_dec->ps_left_mvpred_addr[!u1_pingpong][1].u4_add; 288 WORD8 * p1_refleft0 = (ps_cur_mv_pred + 3)->i1_ref_frame; 289 290 ppv_top_mv_pred_addr[0] = apv_map_ref_idx_to_poc[p1_refTop0[0]]; 291 ppv_top_mv_pred_addr[1] = pu4_map_ref_idx_to_poc_l1[p1_refTop0[1]]; 292 293 ppv_left_mv_pred_addr[2] = apv_map_ref_idx_to_poc[p1_refTop1[0]]; 294 ppv_top_mv_pred_addr[2] = apv_map_ref_idx_to_poc[p1_refTop1[0]]; 295 ppv_left_mv_pred_addr[3] = pu4_map_ref_idx_to_poc_l1[p1_refTop1[1]]; 296 ppv_top_mv_pred_addr[3] = pu4_map_ref_idx_to_poc_l1[p1_refTop1[1]]; 297 298 ppv_left_mv_pred_addr[0] = apv_map_ref_idx_to_poc[p1_refleft0[0]]; 299 ppv_left_mv_pred_addr[1] = pu4_map_ref_idx_to_poc_l1[p1_refleft0[1]]; 300 301 /* Storing the leftMbtype for next Mb */ 302 ps_dec->deblk_left_mb[1].u1_mb_type = ps_cur_mb_params->u1_mb_type; 303 304 } 305 } 306 307 /* For transform 8x8 disable deblocking of the intrernal edges of a 8x8 block */ 308 if(ps_cur_mb_info->u1_tran_form8x8) 309 { 310 pu4_bs_table[1] = 0; 311 pu4_bs_table[3] = 0; 312 pu4_bs_table[5] = 0; 313 pu4_bs_table[7] = 0; 314 } 315 } 316 317 318 void ih264d_check_mb_map_deblk(dec_struct_t *ps_dec, 319 UWORD32 deblk_mb_grp, 320 tfr_ctxt_t *ps_tfr_cxt, 321 UWORD32 u4_check_mb_map) 322 { 323 UWORD32 i = 0; 324 UWORD32 u4_mb_num; 325 UWORD32 u4_cond; 326 volatile UWORD8 *mb_map = ps_dec->pu1_recon_mb_map; 327 const WORD32 i4_cb_qp_idx_ofst = 328 ps_dec->ps_cur_pps->i1_chroma_qp_index_offset; 329 const WORD32 i4_cr_qp_idx_ofst = 330 ps_dec->ps_cur_pps->i1_second_chroma_qp_index_offset; 331 332 UWORD32 u4_wd_y, u4_wd_uv; 333 UWORD8 u1_field_pic_flag = ps_dec->ps_cur_slice->u1_field_pic_flag; 334 335 336 u4_wd_y = ps_dec->u2_frm_wd_y << u1_field_pic_flag; 337 u4_wd_uv = ps_dec->u2_frm_wd_uv << u1_field_pic_flag; 338 339 340 for(i = 0; i < deblk_mb_grp; i++) 341 { 342 WORD32 nop_cnt = 8*128; 343 while(u4_check_mb_map == 1) 344 { 345 u4_mb_num = ps_dec->u4_cur_deblk_mb_num; 346 /*we wait for the right mb because of intra pred data dependency*/ 347 u4_mb_num = MIN(u4_mb_num + 1, (ps_dec->u4_deblk_mb_y + 1) * ps_dec->u2_frm_wd_in_mbs - 1); 348 CHECK_MB_MAP_BYTE(u4_mb_num, mb_map, u4_cond); 349 350 if(u4_cond) 351 { 352 break; 353 } 354 else 355 { 356 if(nop_cnt > 0) 357 { 358 nop_cnt -= 128; 359 NOP(128); 360 } 361 else 362 { 363 nop_cnt = 8*128; 364 ithread_yield(); 365 } 366 } 367 } 368 369 ih264d_deblock_mb_nonmbaff(ps_dec, ps_tfr_cxt, 370 i4_cb_qp_idx_ofst, i4_cr_qp_idx_ofst, 371 u4_wd_y, u4_wd_uv); 372 373 374 } 375 376 377 } 378 void ih264d_recon_deblk_slice(dec_struct_t *ps_dec, tfr_ctxt_t *ps_tfr_cxt) 379 { 380 dec_mb_info_t *p_cur_mb; 381 UWORD32 u4_max_addr; 382 WORD32 i; 383 UWORD32 u1_mb_aff; 384 UWORD16 u2_slice_num; 385 UWORD32 u4_mb_num; 386 UWORD16 u2_first_mb_in_slice; 387 UWORD32 i2_pic_wdin_mbs; 388 UWORD8 u1_num_mbsleft, u1_end_of_row; 389 UWORD8 u1_mbaff; 390 UWORD16 i16_mb_x, i16_mb_y; 391 WORD32 j; 392 dec_mb_info_t * ps_cur_mb_info; 393 UWORD32 u1_slice_type, u1_B; 394 WORD32 u1_skip_th; 395 UWORD32 u1_ipcm_th; 396 WORD32 ret; 397 tfr_ctxt_t *ps_trns_addr; 398 UWORD32 u4_frame_stride; 399 UWORD32 x_offset, y_offset; 400 UWORD32 u4_slice_end; 401 pad_mgr_t *ps_pad_mgr ; 402 403 /*check for mb map of first mb in slice to ensure slice header is parsed*/ 404 while(1) 405 { 406 UWORD32 u4_mb_num = ps_dec->cur_recon_mb_num; 407 UWORD32 u4_cond = 0; 408 WORD32 nop_cnt = 8*128; 409 410 CHECK_MB_MAP_BYTE(u4_mb_num, ps_dec->pu1_recon_mb_map, u4_cond); 411 if(u4_cond) 412 { 413 break; 414 } 415 else 416 { 417 if(nop_cnt > 0) 418 { 419 nop_cnt -= 128; 420 NOP(128); 421 } 422 else 423 { 424 if(ps_dec->u4_output_present && 425 (ps_dec->u4_fmt_conv_cur_row < ps_dec->s_disp_frame_info.u4_y_ht)) 426 { 427 ps_dec->u4_fmt_conv_num_rows = 428 MIN(FMT_CONV_NUM_ROWS, 429 (ps_dec->s_disp_frame_info.u4_y_ht 430 - ps_dec->u4_fmt_conv_cur_row)); 431 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op), 432 ps_dec->u4_fmt_conv_cur_row, 433 ps_dec->u4_fmt_conv_num_rows); 434 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows; 435 } 436 else 437 { 438 nop_cnt = 8*128; 439 ithread_yield(); 440 } 441 } 442 DEBUG_THREADS_PRINTF("waiting for mb mapcur_dec_mb_num = %d,ps_dec->u2_cur_mb_addr = %d\n",u2_cur_dec_mb_num, 443 ps_dec->u2_cur_mb_addr); 444 445 } 446 } 447 448 u4_max_addr = ps_dec->ps_cur_sps->u2_max_mb_addr; 449 u1_mb_aff = ps_dec->ps_cur_slice->u1_mbaff_frame_flag; 450 u2_first_mb_in_slice = ps_dec->ps_computebs_cur_slice->u4_first_mb_in_slice; 451 i2_pic_wdin_mbs = ps_dec->u2_frm_wd_in_mbs; 452 u1_mbaff = ps_dec->ps_cur_slice->u1_mbaff_frame_flag; 453 ps_pad_mgr = &ps_dec->s_pad_mgr; 454 455 if(u2_first_mb_in_slice == 0) 456 ih264d_init_deblk_tfr_ctxt(ps_dec, ps_pad_mgr, ps_tfr_cxt, 457 ps_dec->u2_frm_wd_in_mbs, 0); 458 459 460 i16_mb_x = MOD(u2_first_mb_in_slice, i2_pic_wdin_mbs); 461 i16_mb_y = DIV(u2_first_mb_in_slice, i2_pic_wdin_mbs); 462 i16_mb_y <<= u1_mbaff; 463 ps_dec->i2_recon_thread_mb_y = i16_mb_y; 464 u4_frame_stride = ps_dec->u2_frm_wd_y 465 << ps_dec->ps_cur_slice->u1_field_pic_flag; 466 467 x_offset = i16_mb_x << 4; 468 y_offset = (i16_mb_y * u4_frame_stride) << 4; 469 ps_trns_addr = &ps_dec->s_tran_iprecon; 470 471 ps_trns_addr->pu1_dest_y = ps_dec->s_cur_pic.pu1_buf1 + x_offset + y_offset; 472 473 u4_frame_stride = ps_dec->u2_frm_wd_uv 474 << ps_dec->ps_cur_slice->u1_field_pic_flag; 475 x_offset >>= 1; 476 y_offset = (i16_mb_y * u4_frame_stride) << 3; 477 478 x_offset *= YUV420SP_FACTOR; 479 480 ps_trns_addr->pu1_dest_u = ps_dec->s_cur_pic.pu1_buf2 + x_offset + y_offset; 481 ps_trns_addr->pu1_dest_v = ps_dec->s_cur_pic.pu1_buf3 + x_offset + y_offset; 482 483 ps_trns_addr->pu1_mb_y = ps_trns_addr->pu1_dest_y; 484 ps_trns_addr->pu1_mb_u = ps_trns_addr->pu1_dest_u; 485 ps_trns_addr->pu1_mb_v = ps_trns_addr->pu1_dest_v; 486 487 ps_dec->cur_recon_mb_num = u2_first_mb_in_slice << u1_mbaff; 488 489 u4_slice_end = 0; 490 ps_dec->u4_bs_cur_slice_num_mbs = 0; 491 ps_dec->u4_cur_bs_mb_num = 492 (ps_dec->ps_computebs_cur_slice->u4_first_mb_in_slice) 493 << u1_mb_aff; 494 495 if(ps_dec->i1_recon_in_thread3_flag) 496 { 497 ps_dec->pv_proc_tu_coeff_data = 498 (void *) ps_dec->ps_computebs_cur_slice->pv_tu_coeff_data_start; 499 } 500 501 u1_slice_type = ps_dec->ps_computebs_cur_slice->slice_type; 502 503 u1_B = (u1_slice_type == B_SLICE); 504 505 u1_skip_th = ((u1_slice_type != I_SLICE) ? 506 (u1_B ? B_8x8 : PRED_8x8R0) : -1); 507 508 u1_ipcm_th = ((u1_slice_type != I_SLICE) ? (u1_B ? 23 : 5) : 0); 509 510 511 512 while(u4_slice_end != 1) 513 { 514 WORD32 recon_mb_grp,bs_mb_grp; 515 WORD32 nop_cnt = 8*128; 516 u1_num_mbsleft = ((i2_pic_wdin_mbs - i16_mb_x) << u1_mbaff); 517 if(u1_num_mbsleft <= ps_dec->u1_recon_mb_grp) 518 { 519 recon_mb_grp = u1_num_mbsleft; 520 u1_end_of_row = 1; 521 i16_mb_x = 0; 522 } 523 else 524 { 525 recon_mb_grp = ps_dec->u1_recon_mb_grp; 526 u1_end_of_row = 0; 527 i16_mb_x += (recon_mb_grp >> u1_mbaff); 528 } 529 530 531 while(1) 532 { 533 UWORD32 u4_cond = 0; 534 UWORD32 u4_mb_num = ps_dec->cur_recon_mb_num + recon_mb_grp - 1; 535 536 /* 537 * Wait for one extra mb of MC, because some chroma IQ-IT functions 538 * sometimes loads the pixels of the right mb and stores with the loaded 539 * values. 540 */ 541 u4_mb_num = MIN(u4_mb_num + 1, (ps_dec->i2_recon_thread_mb_y + 1) * i2_pic_wdin_mbs - 1); 542 543 CHECK_MB_MAP_BYTE(u4_mb_num, ps_dec->pu1_recon_mb_map, u4_cond); 544 if(u4_cond) 545 { 546 break; 547 } 548 else 549 { 550 if(nop_cnt > 0) 551 { 552 nop_cnt -= 128; 553 NOP(128); 554 } 555 else 556 { 557 if(ps_dec->u4_output_present && 558 (ps_dec->u4_fmt_conv_cur_row < ps_dec->s_disp_frame_info.u4_y_ht)) 559 { 560 ps_dec->u4_fmt_conv_num_rows = 561 MIN(FMT_CONV_NUM_ROWS, 562 (ps_dec->s_disp_frame_info.u4_y_ht 563 - ps_dec->u4_fmt_conv_cur_row)); 564 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op), 565 ps_dec->u4_fmt_conv_cur_row, 566 ps_dec->u4_fmt_conv_num_rows); 567 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows; 568 } 569 else 570 { 571 nop_cnt = 8*128; 572 ithread_yield(); 573 } 574 } 575 } 576 } 577 578 for(j = 0; j < recon_mb_grp; j++) 579 { 580 GET_SLICE_NUM_MAP(ps_dec->pu2_slice_num_map, ps_dec->cur_recon_mb_num, 581 u2_slice_num); 582 583 if(u2_slice_num != ps_dec->u2_cur_slice_num_bs) 584 { 585 u4_slice_end = 1; 586 break; 587 } 588 if(ps_dec->i1_recon_in_thread3_flag) 589 { 590 ps_cur_mb_info = &ps_dec->ps_frm_mb_info[ps_dec->cur_recon_mb_num]; 591 592 if(ps_cur_mb_info->u1_mb_type <= u1_skip_th) 593 { 594 ih264d_process_inter_mb(ps_dec, ps_cur_mb_info, j); 595 } 596 else if(ps_cur_mb_info->u1_mb_type != MB_SKIP) 597 { 598 if((u1_ipcm_th + 25) != ps_cur_mb_info->u1_mb_type) 599 { 600 ps_cur_mb_info->u1_mb_type -= (u1_skip_th + 1); 601 ih264d_process_intra_mb(ps_dec, ps_cur_mb_info, j); 602 } 603 } 604 605 ih264d_copy_intra_pred_line(ps_dec, ps_cur_mb_info, j); 606 } 607 ps_dec->cur_recon_mb_num++; 608 } 609 610 if(j != recon_mb_grp) 611 { 612 u1_end_of_row = 0; 613 } 614 615 { 616 tfr_ctxt_t *ps_trns_addr = &ps_dec->s_tran_iprecon; 617 UWORD16 u2_mb_y; 618 619 ps_trns_addr->pu1_dest_y += ps_trns_addr->u4_inc_y[u1_end_of_row]; 620 ps_trns_addr->pu1_dest_u += ps_trns_addr->u4_inc_uv[u1_end_of_row]; 621 ps_trns_addr->pu1_dest_v += ps_trns_addr->u4_inc_uv[u1_end_of_row]; 622 623 if(u1_end_of_row) 624 { 625 ps_dec->i2_recon_thread_mb_y += (1 << u1_mbaff); 626 u2_mb_y = ps_dec->i2_recon_thread_mb_y; 627 y_offset = (u2_mb_y * u4_frame_stride) << 4; 628 ps_trns_addr->pu1_dest_y = ps_dec->s_cur_pic.pu1_buf1 + y_offset; 629 630 u4_frame_stride = ps_dec->u2_frm_wd_uv 631 << ps_dec->ps_cur_slice->u1_field_pic_flag; 632 y_offset = (u2_mb_y * u4_frame_stride) << 3; 633 ps_trns_addr->pu1_dest_u = ps_dec->s_cur_pic.pu1_buf2 + y_offset; 634 ps_trns_addr->pu1_dest_v = ps_dec->s_cur_pic.pu1_buf3 + y_offset; 635 636 ps_trns_addr->pu1_mb_y = ps_trns_addr->pu1_dest_y; 637 ps_trns_addr->pu1_mb_u = ps_trns_addr->pu1_dest_u; 638 ps_trns_addr->pu1_mb_v = ps_trns_addr->pu1_dest_v; 639 640 } 641 } 642 643 bs_mb_grp = j; 644 /* Compute BS for NMB group*/ 645 for(i = 0; i < bs_mb_grp; i++) 646 { 647 p_cur_mb = &ps_dec->ps_frm_mb_info[ps_dec->u4_cur_bs_mb_num]; 648 649 DEBUG_THREADS_PRINTF("ps_dec->u4_cur_bs_mb_num = %d\n",ps_dec->u4_cur_bs_mb_num); 650 ih264d_compute_bs_non_mbaff_thread(ps_dec, p_cur_mb, 651 ps_dec->u4_cur_bs_mb_num); 652 ps_dec->u4_cur_bs_mb_num++; 653 ps_dec->u4_bs_cur_slice_num_mbs++; 654 655 } 656 657 if(ps_dec->u4_cur_bs_mb_num > u4_max_addr) 658 { 659 u4_slice_end = 1; 660 } 661 662 /*deblock MB group*/ 663 { 664 UWORD32 u4_num_mbs; 665 666 if(ps_dec->u4_cur_bs_mb_num > ps_dec->u4_cur_deblk_mb_num) 667 { 668 if(u1_end_of_row) 669 { 670 u4_num_mbs = ps_dec->u4_cur_bs_mb_num 671 - ps_dec->u4_cur_deblk_mb_num; 672 } 673 else 674 { 675 u4_num_mbs = ps_dec->u4_cur_bs_mb_num 676 - ps_dec->u4_cur_deblk_mb_num - 1; 677 } 678 } 679 else 680 u4_num_mbs = 0; 681 682 ih264d_check_mb_map_deblk(ps_dec, u4_num_mbs, ps_tfr_cxt,0); 683 } 684 685 } 686 } 687 688 void ih264d_recon_deblk_thread(dec_struct_t *ps_dec) 689 { 690 tfr_ctxt_t s_tfr_ctxt; 691 tfr_ctxt_t *ps_tfr_cxt = &s_tfr_ctxt; // = &ps_dec->s_tran_addrecon; 692 693 694 UWORD32 yield_cnt = 0; 695 696 ithread_set_name("ih264d_recon_deblk_thread"); 697 698 while(1) 699 { 700 701 DEBUG_THREADS_PRINTF(" Entering compute bs slice\n"); 702 ih264d_recon_deblk_slice(ps_dec, ps_tfr_cxt); 703 704 DEBUG_THREADS_PRINTF(" Exit compute bs slice \n"); 705 706 if(ps_dec->cur_recon_mb_num > ps_dec->ps_cur_sps->u2_max_mb_addr) 707 { 708 break; 709 } 710 else 711 { 712 ps_dec->ps_computebs_cur_slice++; 713 ps_dec->u2_cur_slice_num_bs++; 714 } 715 DEBUG_THREADS_PRINTF("CBS thread:Got next slice/end of frame signal \n "); 716 717 } 718 719 if(ps_dec->u4_output_present && 720 (3 == ps_dec->u4_num_cores) && 721 (ps_dec->u4_fmt_conv_cur_row < ps_dec->s_disp_frame_info.u4_y_ht)) 722 { 723 ps_dec->u4_fmt_conv_num_rows = 724 (ps_dec->s_disp_frame_info.u4_y_ht 725 - ps_dec->u4_fmt_conv_cur_row); 726 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op), 727 ps_dec->u4_fmt_conv_cur_row, 728 ps_dec->u4_fmt_conv_num_rows); 729 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows; 730 731 } 732 733 734 735 } 736 737 738
