| /external/llvm/lib/Target/PowerPC/ |
| PPCTargetTransformInfo.cpp | 319 if (ISD == ISD::INSERT_VECTOR_ELT)
327 ISD == ISD::INSERT_VECTOR_ELT)
|
| PPCISelLowering.cpp | 471 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
679 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
729 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 268 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element
271 INSERT_VECTOR_ELT,
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 385 ISD::INSERT_VECTOR_ELT,
396 ISD::INSERT_VECTOR_ELT,
407 ISD::INSERT_VECTOR_ELT,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypesGeneric.cpp | 446 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx);
450 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx);
|
| LegalizeVectorTypes.cpp | 59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
605 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
[all...] |
| SelectionDAGDumper.cpp | 217 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
|
| LegalizeIntegerTypes.cpp | 96 case ISD::INSERT_VECTOR_ELT:
[all...] |
| LegalizeDAG.cpp | 93 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
594 /// INSERT_VECTOR_ELT instruction. In this case, it
[all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 163 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom);
164 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom);
165 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
166 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
172 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
593 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
[all...] |
| SIISelLowering.cpp | 213 case ISD::INSERT_VECTOR_ELT:
237 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
238 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 700 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 101 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
623 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 257 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
306 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | [all...] |
| SystemZISelLowering.cpp | 302 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal);
384 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
385 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 506 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
663 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
