/external/mesa3d/src/gallium/drivers/radeon/ |
AMDGPUSubtarget.h | 40 InstrItineraryData InstrItins; 46 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
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AMDGPUTargetMachine.h | 37 const InstrItineraryData* InstrItins; 62 return InstrItins;
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AMDGPUSubtarget.cpp | 25 InstrItins = getInstrItineraryForCPU(CPU);
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AMDGPUTargetMachine.cpp | 54 InstrItins(&Subtarget.getInstrItineraryData()),
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/external/llvm/lib/CodeGen/ |
TargetSchedule.cpp | 35 return EnableSchedItins && !InstrItins.isEmpty(); 59 STI->initInstrItins(InstrItins); 79 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); 80 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI); 164 OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, 169 OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx); 175 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI); 178 // Rather than directly querying InstrItins stage latency, we call a TII 180 // applicable to the InstrItins model. InstrSchedModel should model all 257 return TII->getInstrLatency(&InstrItins, MI) [all...] |
DFAPacketizer.cpp | 59 InstrItins(I), CurrentState(0), DFAStateInputTable(SIT), 99 for (const InstrStage *IS = InstrItins->beginStage(InsnClass), 100 *IE = InstrItins->endStage(InsnClass); IS != IE; ++IS, ++i) {
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/external/llvm/lib/Target/Hexagon/ |
HexagonSubtarget.h | 56 InstrItineraryData InstrItins; 66 return &InstrItins;
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HexagonSubtarget.cpp | 100 InstrItins = getInstrItineraryForCPU(CPUString);
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/external/llvm/include/llvm/CodeGen/ |
DFAPacketizer.h | 75 const InstrItineraryData *InstrItins; 117 const InstrItineraryData *getInstrItins() const { return InstrItins; }
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TargetSchedule.h | 36 InstrItineraryData InstrItins; 80 return &InstrItins;
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ResourcePriorityQueue.h | 63 const InstrItineraryData* InstrItins;
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/external/llvm/lib/MC/ |
MCSubtargetInfo.cpp | 108 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const { 109 InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,
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/external/llvm/lib/Target/AMDGPU/ |
AMDGPUSubtarget.h | 95 InstrItineraryData InstrItins; 117 return &InstrItins;
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AMDGPUSubtarget.cpp | 79 InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) {
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/external/llvm/lib/Target/Mips/ |
MipsSubtarget.h | 145 InstrItineraryData InstrItins; 307 return &InstrItins;
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MipsSubtarget.cpp | 150 InstrItins = getInstrItineraryForCPU(CPUName);
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/external/llvm/lib/Target/PowerPC/ |
PPCSubtarget.h | 76 InstrItineraryData InstrItins; 160 return &InstrItins;
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PPCSubtarget.cpp | 120 InstrItins = getInstrItineraryForCPU(CPUName);
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/external/llvm/include/llvm/MC/ |
MCSubtargetInfo.h | 159 void initInstrItins(InstrItineraryData &InstrItins) const;
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/external/llvm/lib/CodeGen/SelectionDAG/ |
ScheduleDAGSDNodes.h | 40 const InstrItineraryData *InstrItins;
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ScheduleDAGSDNodes.cpp | 50 InstrItins(mf.getSubtarget().getInstrItineraryData()) {} 608 if (!InstrItins || InstrItins->isEmpty()) { 622 SU->Latency += TII->getInstrLatency(InstrItins, N); 638 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); [all...] |
/external/llvm/lib/Target/ARM/ |
ARMSubtarget.h | 250 InstrItineraryData InstrItins; 474 return &InstrItins;
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ARMSubtarget.cpp | 205 InstrItins = getInstrItineraryForCPU(CPUString);
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/external/llvm/lib/Target/X86/ |
X86Subtarget.h | 247 InstrItineraryData InstrItins; 536 return &InstrItins;
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X86Subtarget.cpp | 211 InstrItins = getInstrItineraryForCPU(CPUName);
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