| /external/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 35 LaneBitmask LaneMask;
38 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU)
39 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
50 VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask,
52 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {}
|
| LiveInterval.h | 593 /// A live range for subregisters. The LaneMask specifies which parts of the
599 LaneBitmask LaneMask;
602 SubRange(LaneBitmask LaneMask)
603 : Next(nullptr), LaneMask(LaneMask) {
607 SubRange(LaneBitmask LaneMask, const LiveRange &Other,
609 : LiveRange(Other, Allocator), Next(nullptr), LaneMask(LaneMask) {
682 LaneBitmask LaneMask) {
683 SubRange *Range = new (Allocator) SubRange(LaneMask);
[all...] |
| MachineBasicBlock.h | 77 LaneBitmask LaneMask;
79 RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
80 : PhysReg(PhysReg), LaneMask(LaneMask) {}
345 void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask = ~0u) {
346 LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
363 void removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask = ~0u);
366 bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask = ~0u) const;
[all...] |
| RegisterScavenging.h | 149 void setRegUsed(unsigned Reg, LaneBitmask LaneMask = ~0u);
|
| LiveIntervalAnalysis.h | 438 /// Only full operands or operands with subregisters matching @p LaneMask
443 unsigned Reg, LaneBitmask LaneMask = ~0u);
|
| /external/llvm/lib/CodeGen/ |
| MachineVerifier.cpp | 217 LaneBitmask LaneMask) const;
237 void verifyLiveRange(const LiveRange&, unsigned, LaneBitmask LaneMask = 0);
443 LaneBitmask LaneMask) const {
445 if (LaneMask != 0)
446 errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
[all...] |
| RegisterCoalescer.cpp | 93 /// A LaneMask to remember on which subregister live ranges we need to call
163 /// LaneMask are split as necessary. @p LaneMask are the lanes that
167 LaneBitmask LaneMask, CoalescerPair &CP);
172 LaneBitmask LaneMask, const CoalescerPair &CP);
804 LaneBitmask AMask = SA.LaneMask;
806 LaneBitmask BMask = SB.LaneMask;
816 SB.LaneMask = BRest;
823 SB.LaneMask = Common;
[all...] |
| VirtRegMap.cpp | 266 LaneBitmask LaneMask = 0;
275 LaneMask |= SR->LaneMask;
277 if (LaneMask == 0)
280 MBB->addLiveIn(PhysReg, LaneMask);
341 if ((SR.LaneMask & UseMask) != 0 && SR.liveAt(BaseIndex))
|
| ScheduleDAGInstrs.cpp | 415 LaneBitmask LaneMask = I->LaneMask;
417 if ((LaneMask & KillLaneMask) == 0) {
422 if ((LaneMask & DefLaneMask) != 0) {
432 LaneMask &= ~KillLaneMask;
434 if (LaneMask != 0) {
435 I->LaneMask = LaneMask;
453 LaneBitmask LaneMask = DefLaneMask;
457 if ((V2SU.LaneMask & LaneMask) == 0
[all...] |
| LiveRangeCalc.h | 132 void extendToUses(LiveRange &LR, unsigned Reg, LaneBitmask LaneMask);
|
| MachineBasicBlock.cpp | 291 if (LI.LaneMask != ~0u)
292 OS << ':' << PrintLaneMask(LI.LaneMask);
335 void MachineBasicBlock::removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) {
342 I->LaneMask &= ~LaneMask;
343 if (I->LaneMask == 0)
347 bool MachineBasicBlock::isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) const {
351 return I != livein_end() && (I->LaneMask & LaneMask) != 0;
365 LaneBitmask LaneMask = I->LaneMask
[all...] |
| LiveIntervalAnalysis.cpp | 545 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg);
546 if ((LaneMask & SR.LaneMask) == 0)
758 DefinedLanesMask |= SR.LaneMask;
[all...] |
| LiveRangeCalc.cpp | 79 LaneBitmask Common = S.LaneMask & Mask;
83 LaneBitmask LRest = S.LaneMask & ~Mask;
87 S.LaneMask = LRest;
90 assert(Common == S.LaneMask);
120 extendToUses(S, Reg, S.LaneMask);
|
| TargetRegisterInfo.cpp | 100 Printable PrintLaneMask(LaneBitmask LaneMask) {
101 return Printable([LaneMask](raw_ostream &OS) {
102 OS << format("%08X", LaneMask);
|
| LiveInterval.cpp | 914 (I->end == Pos && (ActiveMask & SR.LaneMask) == 0)))
918 if ((ActiveMask & SR.LaneMask) == 0 &&
922 EventMask |= SR.LaneMask;
927 EventMask = SR.LaneMask;
931 if ((ActiveMask & SR.LaneMask) != 0 &&
935 EventMask |= SR.LaneMask;
939 EventMask = SR.LaneMask;
[all...] |
| LiveRangeEdit.cpp | 229 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
231 if ((S.LaneMask & LaneMask) != 0 && S.Query(Idx).isKill())
|
| RegisterScavenging.cpp | 34 void RegScavenger::setRegUsed(unsigned Reg, LaneBitmask LaneMask) {
37 if (UnitMask == 0 || (LaneMask & UnitMask) != 0)
57 setRegUsed(LI.PhysReg, LI.LaneMask);
|
| LiveRegMatrix.cpp | 81 if (S.LaneMask & Mask) {
|
| MIRPrinter.cpp | 482 if (LI.LaneMask != ~0u)
483 OS << ':' << PrintLaneMask(LI.LaneMask);
|
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 34 : TheDef(R), EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) {
45 EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) {
87 if (LaneMask)
88 return LaneMask;
91 LaneMask = ~0u;
98 LaneMask = M;
99 return LaneMask;
659 LaneMask(0) {
[all...] |
| CodeGenRegisters.h | 63 mutable unsigned LaneMask;
114 // Compute LaneMask from Composed. Return LaneMask.
311 unsigned LaneMask;
722 // LaneMask is contained in CoveringLanes will be completely covered by
|
| RegisterInfoEmitter.cpp | 732 << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, unsigned LaneMask)"
771 " unsigned Masked = LaneMask & Ops->Mask;\n"
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 68 const LaneBitmask LaneMask;
217 return LaneMask;
541 /// Transforms a LaneMask computed for one subregister to the lanemask that
[all...] |
| /external/llvm/lib/Target/X86/Utils/ |
| X86ShuffleDecode.cpp | 278 unsigned LaneMask = (Imm >> (l * NumControlBits)) & ControlBitsMask;
281 LaneMask += NumLanes;
283 ShuffleMask.push_back(LaneMask * NumElementsInLane + i);
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
