| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 116 const MCOperand &MO1 = MI->getOperand(1);
127 printRegName(O, MO1.getReg());
139 const MCOperand &MO1 = MI->getOperand(1);
149 printRegName(O, MO1.getReg());
362 const MCOperand &MO1 = MI->getOperand(OpNum);
363 if (MO1.isExpr()) {
364 MO1.getExpr()->print(O, &MAI);
370 int32_t OffImm = (int32_t)MO1.getImm();
392 const MCOperand &MO1 = MI->getOperand(OpNum);
396 printRegName(O, MO1.getReg())
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 562 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
566 int32_t SImm = MO1.getImm();
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86OptimizeLEAs.cpp | 69 bool isIdenticalOp(const MachineOperand &MO1, const MachineOperand &MO2);
179 bool OptimizeLEAPass::isIdenticalOp(const MachineOperand &MO1,
181 return MO1.isIdenticalTo(MO2) &&
182 (!MO1.isReg() ||
183 !TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
|
| X86FloatingPoint.cpp | [all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 652 const MachineOperand &MO1 = MI.getOperand(1);
653 unsigned Flags = MO1.getTargetFlags();
661 if (MO1.isGlobal()) {
662 MIB1.addGlobalAddress(MO1.getGlobal(), 0, Flags | AArch64II::MO_PAGE);
663 MIB2.addGlobalAddress(MO1.getGlobal(), 0,
665 } else if (MO1.isSymbol()) {
666 MIB1.addExternalSymbol(MO1.getSymbolName(), Flags | AArch64II::MO_PAGE);
667 MIB2.addExternalSymbol(MO1.getSymbolName(),
670 assert(MO1.isCPI() &&
672 MIB1.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset()
[all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCCodeEmitter.cpp | 267 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
268 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL &&
270 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm());
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 399 MCOperand &MO1 = MappedInst.getOperand(1);
400 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::subreg_hireg);
401 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::subreg_loreg);
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | [all...] |
| ARMExpandPseudoInsts.cpp | [all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | [all...] |
