| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 345 unsigned NewOpc;
348 case X86::CMPPDrmi: NewOpc = X86::CMPPDrmi_alt; break;
349 case X86::CMPPDrri: NewOpc = X86::CMPPDrri_alt; break;
350 case X86::CMPPSrmi: NewOpc = X86::CMPPSrmi_alt; break;
351 case X86::CMPPSrri: NewOpc = X86::CMPPSrri_alt; break;
352 case X86::CMPSDrm: NewOpc = X86::CMPSDrm_alt; break;
353 case X86::CMPSDrr: NewOpc = X86::CMPSDrr_alt; break;
354 case X86::CMPSSrm: NewOpc = X86::CMPSSrm_alt; break;
355 case X86::CMPSSrr: NewOpc = X86::CMPSSrr_alt; break;
356 case X86::VPCOMBri: NewOpc = X86::VPCOMBri_alt; break
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | [all...] |
| Thumb2InstrInfo.cpp | 497 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
498 MI.setDesc(TII.get(NewOpc));
531 unsigned NewOpc = Opcode;
541 NewOpc = immediateOffsetOpcode(Opcode);
553 NewOpc = negativeOffsetOpcode(Opcode);
558 NewOpc = positiveOffsetOpcode(Opcode);
585 if (NewOpc != Opcode)
586 MI.setDesc(TII.get(NewOpc));
619 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
|
| ARMConstantIslandPass.cpp | [all...] |
| ARMExpandPseudoInsts.cpp | [all...] |
| ThumbRegisterInfo.cpp | 398 unsigned NewOpc = convertToNonSPOpcode(Opcode);
399 if (NewOpc != Opcode && FrameReg != ARM::SP)
400 MI.setDesc(TII.get(NewOpc));
|
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.h | 91 unsigned NewOpc) const;
|
| MipsInstrInfo.h | 125 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
|
| MipsSEISelLowering.h | 68 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
|
| MipsInstrInfo.cpp | 278 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
281 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
|
| MipsLongBranch.cpp | 219 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode());
220 const MCInstrDesc &NewDesc = TII->get(NewOpc);
|
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 478 unsigned NewOpc;
481 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
482 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
483 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
484 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
485 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
486 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
487 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
488 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
489 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break
[all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 301 unsigned NewOpc = getTransformOpcode(OldOpc);
302 assert(OldOpc != NewOpc && "transform an instruction to itself?!");
356 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(NewOpc), Dst)
|
| AArch64InstrInfo.cpp | 840 unsigned NewOpc = convertFlagSettingOpcode(CmpInstr);
841 if (NewOpc == Opc)
843 const MCInstrDesc &MCID = get(NewOpc);
873 unsigned NewOpc = MI->getOpcode();
886 case AArch64::ADDWrr: NewOpc = AArch64::ADDSWrr; break;
887 case AArch64::ADDWri: NewOpc = AArch64::ADDSWri; break;
888 case AArch64::ADDXrr: NewOpc = AArch64::ADDSXrr; break;
889 case AArch64::ADDXri: NewOpc = AArch64::ADDSXri; break;
890 case AArch64::ADCWr: NewOpc = AArch64::ADCSWr; break;
891 case AArch64::ADCXr: NewOpc = AArch64::ADCSXr; break
[all...] |
| AArch64LoadStoreOptimizer.cpp | 591 unsigned NewOpc = getMatchingPairOpcode(Opc);
632 TII->get(NewOpc))
726 TII->get(NewOpc))
737 TII->get(NewOpc))
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonGenPredicate.cpp | 370 unsigned NewOpc = getPredForm(Opc);
372 if (NewOpc == 0) {
375 NewOpc = Hexagon::C2_not;
378 NewOpc = TargetOpcode::COPY;
405 MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R);
|
| HexagonBitSimplify.cpp | [all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | [all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelDAGToDAG.cpp | 166 unsigned int NewOpc = AMDGPU::COPY;
168 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, TFI);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 474 unsigned NewOpc;
479 NewOpc = ISD::FP_TO_SINT;
483 NewOpc = ISD::FP_TO_UINT;
489 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| MachineLICM.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIInstrInfo.cpp | 476 int NewOpc;
479 NewOpc = AMDGPU::getCommuteRev(Opcode);
480 if (NewOpc != -1)
482 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
485 NewOpc = AMDGPU::getCommuteOrig(Opcode);
486 if (NewOpc != -1)
488 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
[all...] |
