| /external/llvm/lib/Target/AMDGPU/ |
| SIMachineFunctionInfo.cpp | 31 TIDReg(AMDGPU::NoRegister),
32 ScratchRSrcReg(AMDGPU::NoRegister),
33 ScratchWaveOffsetReg(AMDGPU::NoRegister),
34 PrivateSegmentBufferUserSGPR(AMDGPU::NoRegister),
35 DispatchPtrUserSGPR(AMDGPU::NoRegister),
36 QueuePtrUserSGPR(AMDGPU::NoRegister),
37 KernargSegmentPtrUserSGPR(AMDGPU::NoRegister),
38 DispatchIDUserSGPR(AMDGPU::NoRegister),
39 FlatScratchInitUserSGPR(AMDGPU::NoRegister),
40 PrivateSegmentSizeUserSGPR(AMDGPU::NoRegister),
[all...] |
| AMDGPURegisterInfo.cpp | 27 const MCPhysReg AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
42 return AMDGPU::NoRegister;
|
| SIMachineFunctionInfo.h | 119 bool hasCalculatedTID() const { return TIDReg != AMDGPU::NoRegister; };
247 assert(Reg != AMDGPU::NoRegister && "Should never be unset");
256 assert(Reg != AMDGPU::NoRegister && "Should never be unset");
|
| SIFrameLowering.cpp | 73 assert(ScratchRsrcReg != AMDGPU::NoRegister);
76 assert(ScratchWaveOffsetReg != AMDGPU::NoRegister);
81 unsigned PreloadedPrivateBufferReg = AMDGPU::NoRegister;
|
| SIRegisterInfo.cpp | 108 if (ScratchWaveOffsetReg != AMDGPU::NoRegister) {
114 if (ScratchRSrcReg != AMDGPU::NoRegister) {
225 if (SOffset == AMDGPU::NoRegister) {
285 if (Spill.VGPR == AMDGPU::NoRegister) {
318 if (Spill.VGPR == AMDGPU::NoRegister) {
612 // AMDGPU::NoRegister.
618 return AMDGPU::NoRegister;
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPURegisterInfo.cpp | 31 const uint16_t AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
|
| /art/compiler/jni/quick/x86/ |
| calling_convention_x86.cc | 37 return ManagedRegister::NoRegister(); // No free regs, so assembler uses push/pop
50 return ManagedRegister::NoRegister();
84 ManagedRegister res = ManagedRegister::NoRegister();
96 return ManagedRegister::NoRegister();
110 ManagedRegister res = ManagedRegister::NoRegister();
205 return ManagedRegister::NoRegister();
|
| /art/compiler/jni/quick/arm/ |
| calling_convention_arm.cc | 59 return ArmManagedRegister::NoRegister();
69 return ArmManagedRegister::NoRegister();
85 return ArmManagedRegister::NoRegister();
114 return ManagedRegister::NoRegister();
158 entry_spills_.push_back(ManagedRegister::NoRegister(), 8);
169 entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
188 entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
190 entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
198 entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
|
| /art/compiler/jni/quick/arm64/ |
| calling_convention_arm64.cc | 62 return Arm64ManagedRegister::NoRegister();
96 return ManagedRegister::NoRegister();
129 entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
131 entry_spills_.push_back(ManagedRegister::NoRegister(), 8);
144 entry_spills_.push_back(ManagedRegister::NoRegister(), 8);
146 entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
204 return ManagedRegister::NoRegister();
|
| /art/compiler/jni/quick/mips/ |
| calling_convention_mips.cc | 47 return MipsManagedRegister::NoRegister();
81 return ManagedRegister::NoRegister();
107 entry_spills_.push_back(ManagedRegister::NoRegister(), 8);
114 entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
128 entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
130 entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
138 entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmInstrumentation.cpp | 152 if (Reg != X86::NoRegister)
169 return X86::NoRegister;
174 return Reg == X86::NoRegister ? Reg : getX86SubSuperRegister(Reg, VT);
304 : X86::NoRegister /* ScratchReg */);
425 : X86::NoRegister /* ScratchReg */);
508 if (FrameReg == X86::NoRegister)
537 assert(LocalFrameReg != X86::NoRegister);
541 if (MRI && FrameReg != X86::NoRegister) {
558 if (RegCtx.ScratchReg(MVT::i32) != X86::NoRegister)
567 assert(LocalFrameReg != X86::NoRegister);
[all...] |
| /art/compiler/jni/quick/x86_64/ |
| calling_convention_x86_64.cc | 38 return ManagedRegister::NoRegister(); // No free regs, so assembler uses push/pop
47 return ManagedRegister::NoRegister();
81 ManagedRegister res = ManagedRegister::NoRegister();
172 ManagedRegister res = ManagedRegister::NoRegister();
|
| /art/compiler/jni/quick/mips64/ |
| calling_convention_mips64.cc | 47 return Mips64ManagedRegister::NoRegister();
81 return ManagedRegister::NoRegister();
|
| /art/compiler/utils/ |
| managed_register.h | 64 // It is valid to invoke Equals on and with a NoRegister.
73 static ManagedRegister NoRegister() {
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCChecker.h | 59 s.Register = Hexagon::NoRegister;
65 void setError(unsigned e, unsigned r = Hexagon::NoRegister)
67 void setWarning(unsigned w, unsigned r = Hexagon::NoRegister)
|
| HexagonMCChecker.cpp | 32 HexagonMCChecker::Unconditional(Hexagon::NoRegister, false);
59 unsigned PredReg = Hexagon::NoRegister;
119 S = Hexagon::NoRegister;
|
| /art/compiler/utils/arm/ |
| managed_register_arm_test.cc | 24 TEST(ArmManagedRegister, NoRegister) {
25 ArmManagedRegister reg = ManagedRegister::NoRegister().AsArm();
290 ManagedRegister no_reg = ManagedRegister::NoRegister();
291 EXPECT_TRUE(no_reg.Equals(ArmManagedRegister::NoRegister()));
299 EXPECT_TRUE(!reg_R0.Equals(ArmManagedRegister::NoRegister()));
307 EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::NoRegister()));
317 EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::NoRegister()));
327 EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::NoRegister()));
337 EXPECT_TRUE(!reg_S1.Equals(ArmManagedRegister::NoRegister()));
347 EXPECT_TRUE(!reg_S31.Equals(ArmManagedRegister::NoRegister()));
[all...] |
| /external/llvm/lib/CodeGen/ |
| ImplicitNullChecks.cpp | 352 const unsigned NoRegister = 0; // Guaranteed to be the NoRegister value for
359 unsigned DefReg = NoRegister;
|
| /external/llvm/lib/Target/X86/ |
| X86OptimizeLEAs.cpp | 286 .ChangeToRegister(X86::NoRegister, false);
289 .ChangeToRegister(X86::NoRegister, false);
|
| X86CallFrameOptimization.cpp | 383 (I->getOperand(X86::AddrIndexReg).getReg() != X86::NoRegister) ||
384 (I->getOperand(X86::AddrSegmentReg).getReg() != X86::NoRegister) ||
|
| /art/compiler/utils/arm64/ |
| managed_register_arm64_test.cc | 25 TEST(Arm64ManagedRegister, NoRegister) {
26 Arm64ManagedRegister reg = ManagedRegister::NoRegister().AsArm64();
269 ManagedRegister no_reg = ManagedRegister::NoRegister();
270 EXPECT_TRUE(no_reg.Equals(Arm64ManagedRegister::NoRegister()));
279 EXPECT_TRUE(!reg_X0.Equals(Arm64ManagedRegister::NoRegister()));
287 EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::NoRegister()));
297 EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::NoRegister()));
303 EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::NoRegister()));
313 EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::NoRegister()));
323 EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::NoRegister()));
[all...] |
| /art/compiler/jni/quick/ |
| jni_compiler.cc | 219 ManagedRegister::NoRegister(), false);
266 ManagedRegister::NoRegister(), false);
338 ManagedRegister::NoRegister(), false);
444 ManagedRegister::NoRegister(), false);
561 __ CreateHandleScopeEntry(out_reg, handle_scope_offset, ManagedRegister::NoRegister(), null_allowed);
|
| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 377 assert(Producer != Hexagon::NoRegister);
387 assert(Producer != Hexagon::NoRegister);
574 if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister)
586 Hexagon::C1_0, Hexagon::NoRegister,
587 Hexagon::C3_2, Hexagon::NoRegister,
588 Hexagon::C7_6, Hexagon::NoRegister,
589 Hexagon::C9_8, Hexagon::NoRegister,
590 Hexagon::C11_10, Hexagon::NoRegister,
591 Hexagon::CS, Hexagon::NoRegister,
592 Hexagon::UPC, Hexagon::NoRegister
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCMCInstLower.cpp | 187 assert(MO.getReg() > PPC::NoRegister &&
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCTargetDesc.cpp | 71 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
|
