1 /* CPU data header for xstormy16. 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5 Copyright (C) 1996-2014 Free Software Foundation, Inc. 6 7 This file is part of the GNU Binutils and/or GDB, the GNU debugger. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22 23 */ 24 25 #ifndef XSTORMY16_CPU_H 26 #define XSTORMY16_CPU_H 27 28 #define CGEN_ARCH xstormy16 29 30 /* Given symbol S, return xstormy16_cgen_<S>. */ 31 #define CGEN_SYM(s) xstormy16##_cgen_##s 32 33 34 /* Selected cpu families. */ 35 #define HAVE_CPU_XSTORMY16 36 37 #define CGEN_INSN_LSB0_P 0 38 39 /* Minimum size of any insn (in bytes). */ 40 #define CGEN_MIN_INSN_SIZE 2 41 42 /* Maximum size of any insn (in bytes). */ 43 #define CGEN_MAX_INSN_SIZE 4 44 45 #define CGEN_INT_INSN_P 1 46 47 /* Maximum number of syntax elements in an instruction. */ 48 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19 49 50 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. 51 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands 52 we can't hash on everything up to the space. */ 53 #define CGEN_MNEMONIC_OPERANDS 54 55 /* Maximum number of fields in an instruction. */ 56 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 9 57 58 /* Enums. */ 59 60 /* Enum declaration for . */ 61 typedef enum gr_names { 62 H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3 63 , H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7 64 , H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11 65 , H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15 66 , H_GR_PSW = 14, H_GR_SP = 15 67 } GR_NAMES; 68 69 /* Enum declaration for . */ 70 typedef enum gr_rb_names { 71 H_RBJ_R8 = 0, H_RBJ_R9 = 1, H_RBJ_R10 = 2, H_RBJ_R11 = 3 72 , H_RBJ_R12 = 4, H_RBJ_R13 = 5, H_RBJ_R14 = 6, H_RBJ_R15 = 7 73 , H_RBJ_PSW = 6, H_RBJ_SP = 7 74 } GR_RB_NAMES; 75 76 /* Enum declaration for insn op enums. */ 77 typedef enum insn_op1 { 78 OP1_0, OP1_1, OP1_2, OP1_3 79 , OP1_4, OP1_5, OP1_6, OP1_7 80 , OP1_8, OP1_9, OP1_A, OP1_B 81 , OP1_C, OP1_D, OP1_E, OP1_F 82 } INSN_OP1; 83 84 /* Enum declaration for insn op enums. */ 85 typedef enum insn_op2 { 86 OP2_0, OP2_1, OP2_2, OP2_3 87 , OP2_4, OP2_5, OP2_6, OP2_7 88 , OP2_8, OP2_9, OP2_A, OP2_B 89 , OP2_C, OP2_D, OP2_E, OP2_F 90 } INSN_OP2; 91 92 /* Enum declaration for insn op enums. */ 93 typedef enum insn_op2a { 94 OP2A_0, OP2A_2, OP2A_4, OP2A_6 95 , OP2A_8, OP2A_A, OP2A_C, OP2A_E 96 } INSN_OP2A; 97 98 /* Enum declaration for insn op enums. */ 99 typedef enum insn_op2m { 100 OP2M_0, OP2M_1 101 } INSN_OP2M; 102 103 /* Enum declaration for insn op enums. */ 104 typedef enum insn_op3 { 105 OP3_0, OP3_1, OP3_2, OP3_3 106 , OP3_4, OP3_5, OP3_6, OP3_7 107 , OP3_8, OP3_9, OP3_A, OP3_B 108 , OP3_C, OP3_D, OP3_E, OP3_F 109 } INSN_OP3; 110 111 /* Enum declaration for insn op enums. */ 112 typedef enum insn_op3a { 113 OP3A_0, OP3A_1, OP3A_2, OP3A_3 114 } INSN_OP3A; 115 116 /* Enum declaration for insn op enums. */ 117 typedef enum insn_op3b { 118 OP3B_0, OP3B_2, OP3B_4, OP3B_6 119 , OP3B_8, OP3B_A, OP3B_C, OP3B_E 120 } INSN_OP3B; 121 122 /* Enum declaration for insn op enums. */ 123 typedef enum insn_op4 { 124 OP4_0, OP4_1, OP4_2, OP4_3 125 , OP4_4, OP4_5, OP4_6, OP4_7 126 , OP4_8, OP4_9, OP4_A, OP4_B 127 , OP4_C, OP4_D, OP4_E, OP4_F 128 } INSN_OP4; 129 130 /* Enum declaration for insn op enums. */ 131 typedef enum insn_op4m { 132 OP4M_0, OP4M_1 133 } INSN_OP4M; 134 135 /* Enum declaration for insn op enums. */ 136 typedef enum insn_op4b { 137 OP4B_0, OP4B_1 138 } INSN_OP4B; 139 140 /* Enum declaration for insn op enums. */ 141 typedef enum insn_op5 { 142 OP5_0, OP5_1, OP5_2, OP5_3 143 , OP5_4, OP5_5, OP5_6, OP5_7 144 , OP5_8, OP5_9, OP5_A, OP5_B 145 , OP5_C, OP5_D, OP5_E, OP5_F 146 } INSN_OP5; 147 148 /* Enum declaration for insn op enums. */ 149 typedef enum insn_op5a { 150 OP5A_0, OP5A_1 151 } INSN_OP5A; 152 153 /* Attributes. */ 154 155 /* Enum declaration for machine type selection. */ 156 typedef enum mach_attr { 157 MACH_BASE, MACH_XSTORMY16, MACH_MAX 158 } MACH_ATTR; 159 160 /* Enum declaration for instruction set selection. */ 161 typedef enum isa_attr { 162 ISA_XSTORMY16, ISA_MAX 163 } ISA_ATTR; 164 165 /* Number of architecture variants. */ 166 #define MAX_ISAS 1 167 #define MAX_MACHS ((int) MACH_MAX) 168 169 /* Ifield support. */ 170 171 /* Ifield attribute indices. */ 172 173 /* Enum declaration for cgen_ifld attrs. */ 174 typedef enum cgen_ifld_attr { 175 CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED 176 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 177 , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS 178 } CGEN_IFLD_ATTR; 179 180 /* Number of non-boolean elements in cgen_ifld_attr. */ 181 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) 182 183 /* cgen_ifld attribute accessor macros. */ 184 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) 185 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) 186 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) 187 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) 188 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) 189 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) 190 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) 191 192 /* Enum declaration for xstormy16 ifield types. */ 193 typedef enum ifield_type { 194 XSTORMY16_F_NIL, XSTORMY16_F_ANYOF, XSTORMY16_F_RD, XSTORMY16_F_RDM 195 , XSTORMY16_F_RM, XSTORMY16_F_RS, XSTORMY16_F_RB, XSTORMY16_F_RBJ 196 , XSTORMY16_F_OP1, XSTORMY16_F_OP2, XSTORMY16_F_OP2A, XSTORMY16_F_OP2M 197 , XSTORMY16_F_OP3, XSTORMY16_F_OP3A, XSTORMY16_F_OP3B, XSTORMY16_F_OP4 198 , XSTORMY16_F_OP4M, XSTORMY16_F_OP4B, XSTORMY16_F_OP5, XSTORMY16_F_OP5A 199 , XSTORMY16_F_OP, XSTORMY16_F_IMM2, XSTORMY16_F_IMM3, XSTORMY16_F_IMM3B 200 , XSTORMY16_F_IMM4, XSTORMY16_F_IMM8, XSTORMY16_F_IMM12, XSTORMY16_F_IMM16 201 , XSTORMY16_F_LMEM8, XSTORMY16_F_HMEM8, XSTORMY16_F_REL8_2, XSTORMY16_F_REL8_4 202 , XSTORMY16_F_REL12, XSTORMY16_F_REL12A, XSTORMY16_F_ABS24_1, XSTORMY16_F_ABS24_2 203 , XSTORMY16_F_ABS24, XSTORMY16_F_MAX 204 } IFIELD_TYPE; 205 206 #define MAX_IFLD ((int) XSTORMY16_F_MAX) 207 208 /* Hardware attribute indices. */ 209 210 /* Enum declaration for cgen_hw attrs. */ 211 typedef enum cgen_hw_attr { 212 CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE 213 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS 214 } CGEN_HW_ATTR; 215 216 /* Number of non-boolean elements in cgen_hw_attr. */ 217 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) 218 219 /* cgen_hw attribute accessor macros. */ 220 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) 221 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) 222 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) 223 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) 224 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) 225 226 /* Enum declaration for xstormy16 hardware types. */ 227 typedef enum cgen_hw_type { 228 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR 229 , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_RB 230 , HW_H_RBJ, HW_H_RPSW, HW_H_Z8, HW_H_Z16 231 , HW_H_CY, HW_H_HC, HW_H_OV, HW_H_PT 232 , HW_H_S, HW_H_BRANCHCOND, HW_H_WORDSIZE, HW_MAX 233 } CGEN_HW_TYPE; 234 235 #define MAX_HW ((int) HW_MAX) 236 237 /* Operand attribute indices. */ 238 239 /* Enum declaration for cgen_operand attrs. */ 240 typedef enum cgen_operand_attr { 241 CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT 242 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY 243 , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS 244 } CGEN_OPERAND_ATTR; 245 246 /* Number of non-boolean elements in cgen_operand_attr. */ 247 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) 248 249 /* cgen_operand attribute accessor macros. */ 250 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) 251 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) 252 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) 253 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) 254 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) 255 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) 256 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) 257 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) 258 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) 259 260 /* Enum declaration for xstormy16 operand types. */ 261 typedef enum cgen_operand_type { 262 XSTORMY16_OPERAND_PC, XSTORMY16_OPERAND_PSW_Z8, XSTORMY16_OPERAND_PSW_Z16, XSTORMY16_OPERAND_PSW_CY 263 , XSTORMY16_OPERAND_PSW_HC, XSTORMY16_OPERAND_PSW_OV, XSTORMY16_OPERAND_PSW_PT, XSTORMY16_OPERAND_PSW_S 264 , XSTORMY16_OPERAND_RD, XSTORMY16_OPERAND_RDM, XSTORMY16_OPERAND_RM, XSTORMY16_OPERAND_RS 265 , XSTORMY16_OPERAND_RB, XSTORMY16_OPERAND_RBJ, XSTORMY16_OPERAND_BCOND2, XSTORMY16_OPERAND_WS2 266 , XSTORMY16_OPERAND_BCOND5, XSTORMY16_OPERAND_IMM2, XSTORMY16_OPERAND_IMM3, XSTORMY16_OPERAND_IMM3B 267 , XSTORMY16_OPERAND_IMM4, XSTORMY16_OPERAND_IMM8, XSTORMY16_OPERAND_IMM8SMALL, XSTORMY16_OPERAND_IMM12 268 , XSTORMY16_OPERAND_IMM16, XSTORMY16_OPERAND_LMEM8, XSTORMY16_OPERAND_HMEM8, XSTORMY16_OPERAND_REL8_2 269 , XSTORMY16_OPERAND_REL8_4, XSTORMY16_OPERAND_REL12, XSTORMY16_OPERAND_REL12A, XSTORMY16_OPERAND_ABS24 270 , XSTORMY16_OPERAND_PSW, XSTORMY16_OPERAND_RPSW, XSTORMY16_OPERAND_SP, XSTORMY16_OPERAND_R0 271 , XSTORMY16_OPERAND_R1, XSTORMY16_OPERAND_R2, XSTORMY16_OPERAND_R8, XSTORMY16_OPERAND_MAX 272 } CGEN_OPERAND_TYPE; 273 274 /* Number of operands types. */ 275 #define MAX_OPERANDS 39 276 277 /* Maximum number of operands referenced by any insn. */ 278 #define MAX_OPERAND_INSTANCES 8 279 280 /* Insn attribute indices. */ 281 282 /* Enum declaration for cgen_insn attrs. */ 283 typedef enum cgen_insn_attr { 284 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI 285 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED 286 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 287 , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS 288 } CGEN_INSN_ATTR; 289 290 /* Number of non-boolean elements in cgen_insn_attr. */ 291 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) 292 293 /* cgen_insn attribute accessor macros. */ 294 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) 295 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) 296 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) 297 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) 298 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) 299 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) 300 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) 301 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) 302 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) 303 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) 304 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) 305 306 /* cgen.h uses things we just defined. */ 307 #include "opcode/cgen.h" 308 309 extern const struct cgen_ifld xstormy16_cgen_ifld_table[]; 310 311 /* Attributes. */ 312 extern const CGEN_ATTR_TABLE xstormy16_cgen_hardware_attr_table[]; 313 extern const CGEN_ATTR_TABLE xstormy16_cgen_ifield_attr_table[]; 314 extern const CGEN_ATTR_TABLE xstormy16_cgen_operand_attr_table[]; 315 extern const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[]; 316 317 /* Hardware decls. */ 318 319 extern CGEN_KEYWORD xstormy16_cgen_opval_gr_names; 320 extern CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names; 321 extern CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names; 322 extern CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond; 323 extern CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize; 324 325 extern const CGEN_HW_ENTRY xstormy16_cgen_hw_table[]; 326 327 328 329 #endif /* XSTORMY16_CPU_H */ 330
