| /external/llvm/include/llvm/CodeGen/ |
| LiveRegMatrix.h | 20 // in the physreg.
84 /// assigned to PhysReg or its aliases. This interference could be resolved
94 /// regmask operand that doesn't preserve PhysReg. This typically means
95 /// VirtReg is live across a call, and PhysReg isn't call-preserved.
99 /// Check for interference before assigning VirtReg to PhysReg.
100 /// If this function returns IK_Free, it is legal to assign(VirtReg, PhysReg).
103 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg);
105 /// Assign VirtReg to PhysReg.
107 /// update VirtRegMap. The live range is expected to be available in PhysReg.
108 void assign(LiveInterval &VirtReg, unsigned PhysReg);
[all...] |
| RegisterClassInfo.h | 108 /// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR.
109 unsigned getLastCalleeSavedAlias(unsigned PhysReg) const {
110 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
111 if (unsigned N = CSRNum[PhysReg])
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| MachineRegisterInfo.h | 540 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
542 /// a physreg.
543 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
594 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
637 bool isPhysRegModified(unsigned PhysReg) const;
643 bool isPhysRegUsed(unsigned PhysReg) const;
677 /// canReserveReg - Returns true if PhysReg can be used as a reserved
680 bool canReserveReg(unsigned PhysReg) const {
681 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
694 /// isReserved - Returns true when PhysReg is a reserved register
[all...] |
| MachineOperand.h | 471 /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
475 static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
477 assert(PhysReg < (1u << 30) && "Not a physical register");
478 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
481 /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
482 bool clobbersPhysReg(unsigned PhysReg) const {
483 return clobbersPhysReg(getRegMask(), PhysReg);
687 /// mask has a bit set for each physreg that is preserved by this
691 /// Any physreg with a 0 bit in the mask is clobbered by the instruction
[all...] |
| MachineBasicBlock.h | 76 MCPhysReg PhysReg;
79 RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
80 : PhysReg(PhysReg), LaneMask(LaneMask) {}
345 void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask = ~0u) {
346 LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
357 /// Add PhysReg as live in to this block, and ensure that there is a copy of
358 /// PhysReg to a virtual register of class RC. Return the virtual register
359 /// that is a copy of the live in PhysReg.
360 unsigned addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC)
[all...] |
| /external/llvm/lib/CodeGen/ |
| RegAllocFast.cpp | 73 unsigned PhysReg; // Currently held here.
78 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){}
123 // Mark a physreg as used in this instruction.
124 void markRegUsedInInstr(unsigned PhysReg) {
125 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
129 // Check if a physreg or any of its aliases are used in this instruction.
130 bool isRegUsedInInstr(unsigned PhysReg) const {
131 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
177 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
178 unsigned calcSpillCost(unsigned PhysReg) const
[all...] |
| LiveRegMatrix.cpp | 75 unsigned PhysReg, Callable Func) {
77 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
89 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
97 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) {
99 << " to " << PrintReg(PhysReg, TRI) << ':');
101 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
103 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
115 unsigned PhysReg = VRM->getPhys(VirtReg.reg);
117 << " from " << PrintReg(PhysReg, TRI) << ':');
120 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit
[all...] |
| RegisterClassInfo.cpp | 99 unsigned PhysReg = RawOrder[i];
101 if (Reserved.test(PhysReg))
103 unsigned Cost = TRI->getCostPerUse(PhysReg);
106 if (CSRNum[PhysReg])
107 // PhysReg aliases a CSR, save it for later.
108 CSRAlias.push_back(PhysReg);
112 RCI.Order[N++] = PhysReg;
121 unsigned PhysReg = CSRAlias[i];
122 unsigned Cost = TRI->getCostPerUse(PhysReg);
125 RCI.Order[N++] = PhysReg;
[all...] |
| AllocationOrder.h | 81 /// Return true if PhysReg is a preferred register.
82 bool isHint(unsigned PhysReg) const {
83 return std::find(Hints.begin(), Hints.end(), PhysReg) != Hints.end();
|
| InterferenceCache.h | 39 /// of PhysReg in all basic blocks.
41 /// PhysReg - The register currently represented.
42 unsigned PhysReg;
63 /// RegUnitInfo - Information tracked about each RegUnit in PhysReg.
86 /// Info for each RegUnit in PhysReg. It is very rare ofr a PHysReg to have
97 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(nullptr), LIS(nullptr) {}
101 PhysReg = 0;
107 unsigned getPhysReg() const { return PhysReg; }
115 /// valid - Return true if this is a valid entry for physReg
[all...] |
| RegisterCoalescer.h | 55 /// is a physreg. This register class may be a super-register of both
64 /// Create a CoalescerPair representing a virtreg-to-physreg copy.
66 CoalescerPair(unsigned VirtReg, unsigned PhysReg,
68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
|
| LiveRangeCalc.h | 113 /// PhysReg, when set, is used to verify live-in lists on basic blocks.
115 SlotIndex Kill, unsigned PhysReg);
171 /// PhysReg, when set, is used to verify live-in lists on basic blocks.
172 void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg = 0);
183 void extendToUses(LiveRange &LR, unsigned PhysReg) {
184 extendToUses(LR, PhysReg, ~0u);
|
| RegAllocGreedy.cpp | 261 unsigned PhysReg;
266 // Interference for PhysReg.
274 PhysReg = Reg;
294 /// Candidate info for each PhysReg in AllocationOrder.
355 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
360 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
382 unsigned PhysReg, unsigned &CostPerUseLimit,
408 /// In case of a physical register Reg == PhysReg.
409 unsigned PhysReg;
410 HintInfo(BlockFrequency Freq, unsigned Reg, unsigned PhysReg)
[all...] |
| VirtRegMap.cpp | 170 void addLiveInsForSubRanges(const LiveInterval &LI, unsigned PhysReg) const;
242 unsigned PhysReg) const {
280 MBB->addLiveIn(PhysReg, LaneMask);
295 // assigned PhysReg must be marked as live-in to those blocks.
296 unsigned PhysReg = VRM->getPhys(VirtReg);
297 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
300 addLiveInsForSubRanges(LI, PhysReg);
310 MBB->addLiveIn(PhysReg);
316 // Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
372 unsigned PhysReg = VRM->getPhys(VirtReg)
[all...] |
| InterferenceCache.cpp | 56 InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) {
57 unsigned E = PhysRegEntries[PhysReg];
58 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) {
74 Entries[E].reset(PhysReg, LIUArray, TRI, MF);
75 PhysRegEntries[PhysReg] = E;
89 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i)
93 void InterferenceCache::Entry::reset(unsigned physReg,
100 PhysReg = physReg;
106 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
[all...] |
| RegAllocBasic.cpp | 111 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
163 // Spill or split all live virtual registers currently unified under PhysReg
166 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
173 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
185 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
189 // Spill each interfering vreg allocated to PhysReg or an alias.
227 while (unsigned PhysReg = Order.next()) {
228 // Check for interference in PhysReg
229 switch (Matrix->checkInterference(VirtReg, PhysReg)) {
231 // PhysReg is available, allocate it
[all...] |
| MachineRegisterInfo.cpp | 106 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
417 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
419 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
423 for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true);
474 bool MachineRegisterInfo::isPhysRegModified(unsigned PhysReg) const {
475 if (UsedPhysRegMask.test(PhysReg))
478 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
488 bool MachineRegisterInfo::isPhysRegUsed(unsigned PhysReg) const {
489 if (UsedPhysRegMask.test(PhysReg))
492 for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid()
[all...] |
| LiveRangeCalc.cpp | 223 void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg) {
239 if (findReachingDefs(LR, *UseMBB, Use, PhysReg))
259 SlotIndex Use, unsigned PhysReg) {
276 errs() << "Use of " << PrintReg(PhysReg)
284 if (TargetRegisterInfo::isPhysicalRegister(PhysReg) &&
285 !MBB->isLiveIn(PhysReg)) {
287 errs() << "The register " << PrintReg(PhysReg)
|
| MachineBasicBlock.cpp | 290 OS << ' ' << PrintReg(LI.PhysReg, TRI);
338 [Reg] (const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
350 [Reg] (const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
357 return LI0.PhysReg < LI1.PhysReg;
359 // Liveins are sorted by physreg now we can merge their lanemasks.
364 unsigned PhysReg = I->PhysReg;
366 for (J = std::next(I); J != LiveIns.end() && J->PhysReg == PhysReg; ++J
[all...] |
| ShrinkWrap.cpp | 232 unsigned PhysReg = MO.getReg();
233 if (!PhysReg)
235 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) &&
237 UseOrDefCSR = RCI.getLastCalleeSavedAlias(PhysReg);
|
| DeadMachineInstructionElim.cpp | 77 // Don't delete live physreg defs, or any reserved register defs.
114 LivePhysRegs.set(LI.PhysReg);
116 // Now scan the instructions and delete dead ones, tracking physreg
137 // Record the physreg defs.
155 // Record the physreg uses, after the defs, in case a physreg is
|
| LivePhysRegs.cpp | 132 LiveRegs.addReg(LI.PhysReg);
|
| /external/llvm/utils/TableGen/ |
| FastISelEmitter.cpp | 426 std::string PhysReg;
429 return PhysReg;
433 return PhysReg;
435 PhysReg += cast<StringInit>(OpLeafRec->getValue("Namespace")->getValue())
437 PhysReg += "::";
438 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName();
439 return PhysReg;
542 std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target);
543 if (PhysReg.empty()) {
553 PhysRegInputs->push_back(PhysReg);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.cpp | 113 unsigned &PhysReg, int &Cost) {
124 PhysReg = Reg;
129 PhysReg = Reg;
132 if (PhysReg != 0) {
466 unsigned PhysReg = 0;
469 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
470 assert((PhysReg == 0 || !isChain) &&
471 "Chain dependence via physreg data?");
478 PhysReg = 0;
487 : SDep(OpSU, SDep::Data, PhysReg);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCFGOptimizer.cpp | 217 LayoutSucc->removeLiveIn(OrigLI.PhysReg);
|
