| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| addthumb2err.s | 13 add sp, sp, r0, RRX
18 adds sp, sp, r0, RRX
23 sub sp, sp, r0, RRX
28 subs sp, sp, r0, RRX
|
| addthumb2err.l | 6 [^:]*:13: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,RRX'
11 [^:]*:18: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,RRX'
16 [^:]*:23: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,RRX'
21 [^:]*:28: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,RRX'
|
| inst.s | 11 mov r14, r15, rrx
206 mov r1, r2, rrx
222 mov r1, r2, RRX
|
| thumb2_bad_reg.s | 391 @ RRX
392 rrx r13, r0
393 rrx r15, r0
394 rrx r0, r13
395 rrx r0, r15
|
| /art/compiler/utils/arm/ |
| constants_arm.h | 163 RRX = 4, // Rotate right with extend.
|
| assembler_arm.cc | 102 case arm::Shift::RRX:
141 if (shift_ == RRX) {
143 // RRX is encoded as an ROR with imm 0.
181 if (shift == RRX) {
[all...] |
| assembler_arm32_test.cc | 170 arm::Shift::LSL, arm::Shift::LSR, arm::Shift::ASR, arm::Shift::ROR, arm::Shift::RRX
179 if (shift != arm::Shift::RRX) {
195 // RRX doesn't have an immediate.
269 if (sop.GetShift() == arm::Shift::RRX) {
|
| assembler_thumb2.cc | [all...] |
| /external/v8/src/arm/ |
| constants-arm.h | 262 // RRX is encoded as ROR with shift_imm == 0.
263 // Use a special code to make the distinction. The RRX ShiftOp is only used
266 RRX = -1,
|
| assembler-arm.cc | 299 // RRX as ROR #0 (See below).
301 } else if (shift_op == RRX) {
311 DCHECK(shift_op != RRX);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 68 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
|
| ARMExpandPseudoInsts.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /art/compiler/utils/ |
| assembler_thumb_test.cc | 444 // 32-bit RRX because RRX has no 16-bit version.
445 __ movs(R3, ShifterOperand(R4, RRX));
452 __ mov(R3, ShifterOperand(R4, RRX), AL, kCcKeep);
459 __ movs(R8, ShifterOperand(R4, RRX));
476 // 32-bit RRX because RRX has no 16-bit version.
477 __ Rrx(R3, R4);
484 __ Rrx(R3, R4, AL, kCcKeep);
[all...] |
| /external/llvm/test/MC/ARM/ |
| basic-arm-instructions.s | 86 adc r4, r5, r6, rrx
100 adc r4, r5, rrx
105 adc r4, r5, rrx
124 @ CHECK: adc r4, r5, r6, rrx @ encoding: [0x66,0x40,0xa5,0xe0]
137 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
142 @ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
205 add r4, r5, r6, rrx
229 add r4, r5, rrx
261 @ CHECK: add r4, r5, r6, rrx @ encoding: [0x66,0x40,0x85,0xe0]
284 @ CHECK: add r4, r4, r5, rrx @ encoding: [0x65,0x40,0x84,0xe0
[all...] |
| basic-thumb2-instructions.s | [all...] |
