| /external/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 113 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
142 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
144 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
145 return scavengeRegister(RegClass, MBBI, SPAdj);
|
| RegisterClassInfo.h | 45 std::unique_ptr<RCInfo[]> RegClass;
71 const RCInfo &RCI = RegClass[RC->getID()];
|
| MachineRegisterInfo.h | 588 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
[all...] |
| /external/llvm/lib/CodeGen/ |
| RegisterClassInfo.cpp | 42 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
81 RCInfo &RCI = RegClass[RC->getID()];
117 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
|
| MachineRegisterInfo.cpp | 91 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
92 assert(RegClass && "Cannot create register without RegClass!");
93 assert(RegClass->isAllocatable() &&
94 "Virtual register RegClass must be allocatable.");
99 VRegInfo[Reg].first = RegClass;
|
| TargetInstrInfo.cpp | 50 short RegClass = MCID.OpInfo[OpNum].RegClass;
52 return TRI->getPointerRegClass(MF, RegClass);
55 if (RegClass < 0)
59 return TRI->getRegClass(RegClass);
[all...] |
| LiveIntervalAnalysis.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64DeadRegisterDefinitionsPass.cpp | 111 switch (MI.getDesc().OpInfo[i].RegClass) {
|
| AArch64A57FPLoadBalancing.cpp | 500 unsigned RegClassID = G->getStart()->getDesc().OpInfo[0].RegClass;
|
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 203 int RCID = Desc.OpInfo[i].RegClass;
265 int RCID = Desc.OpInfo[OpNo].RegClass;
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIFoldOperands.cpp | 227 TRI.getRegClass(FoldDesc.OpInfo[0].RegClass);
286 UseDesc.OpInfo[UseOpIdx].RegClass == -1)
|
| SIInstrInfo.h | 349 if (OpInfo.RegClass == -1) {
355 return RI.getRegClass(OpInfo.RegClass)->getSize();
|
| SIInstrInfo.cpp | [all...] |
| AMDGPUISelDAGToDAG.cpp | 191 int RegClass = Desc.OpInfo[OpIdx].RegClass;
192 if (RegClass == -1)
195 return Subtarget->getRegisterInfo()->getRegClass(RegClass);
359 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
363 N->getOperand(0), RegClass);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 545 const TargetRegisterClass *RegClass = &X86::GR64RegClass;
547 : MRI.createVirtualRegister(RegClass),
549 : MRI.createVirtualRegister(RegClass),
551 : MRI.createVirtualRegister(RegClass),
553 : MRI.createVirtualRegister(RegClass),
555 : MRI.createVirtualRegister(RegClass),
557 : MRI.createVirtualRegister(RegClass),
559 : MRI.createVirtualRegister(RegClass),
561 : MRI.createVirtualRegister(RegClass),
563 : MRI.createVirtualRegister(RegClass);
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCInstrDesc.h | 62 int16_t RegClass;
|
| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 311 int RCID = Desc.OpInfo[OpNo].RegClass;
334 const MCRegisterClass &ImmRC = MRI.getRegClass(Desc.OpInfo[OpNo].RegClass);
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMLoadStoreOptimizer.cpp | 132 unsigned findFreeReg(const TargetRegisterClass &RegClass);
534 /// Return the first register of class \p RegClass that is not in \p Regs.
535 unsigned ARMLoadStoreOpt::findFreeReg(const TargetRegisterClass &RegClass) {
541 for (unsigned Reg : RegClassInfo.getOrder(&RegClass))
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 695 // Verify that all altorder members are regclass members.
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 253 switch (MI->getDesc().OpInfo->RegClass) {
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 279 unsigned &RegClass, unsigned &Cost,
292 RegClass = RC->getID();
301 RegClass = RC->getID();
309 RegClass = RC->getID();
314 RegClass = TLI->getRepRegClassFor(VT)->getID();
[all...] |
| FastISel.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | [all...] |
