| /external/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 259 case ISD::SUBE:
264 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
|
| MipsSEISelDAGToDAG.cpp | 241 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
718 case ISD::SUBE: {
[all...] |
| MipsSEISelLowering.cpp | 143 setTargetDAGCombine(ISD::SUBE);
458 // (addc Lo0, multLo), (sube Hi0, multHi),
515 // replace uses of sube and subc here
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 223 ADDE, SUBE,
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 73 SUBE, // Sub using carry
|
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 234 case ISD::SUBE: return "sube";
|
| LegalizeIntegerTypes.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 130 setOperationAction(ISD::SUBE, MVT::i64, Expand);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 154 ISD::SUBE}) {
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 111 setOperationAction(ISD::SUBE, VT, Expand);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 96 setOperationAction(ISD::SUBE, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 209 setOperationAction(ISD::SUBE, MVT::i32, Custom);
213 setOperationAction(ISD::SUBE, MVT::i64, Custom);
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 187 setOperationAction(ISD::SUBE, VT, Expand);
[all...] |
| SIISelLowering.cpp | 78 setOperationAction(ISD::SUBE, MVT::i32, Legal);
[all...] |
| AMDGPUISelLowering.cpp | 322 setOperationAction(ISD::SUBE, VT, Expand);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 291 setOperationAction(ISD::SUBE, VT, Custom);
[all...] |
