| /external/llvm/include/llvm/Target/ |
| TargetOpcodes.h | 54 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
58 SUBREG_TO_REG = 9,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCVSXCopy.cpp | 118 TII->get(TargetOpcode::SUBREG_TO_REG), NewVReg)
|
| PPCVSXSwapRemoval.cpp | 133 // Hunt backwards through COPY and SUBREG_TO_REG chains for a
290 // Unfortunately, MachineCSE ignores COPY and SUBREG_TO_REG, so we
291 // can also see XXPERMDI t, SUBREG_TO_REG(s), SUBREG_TO_REG(s), 2,
293 // SUBREG_TO_REG to find the real source value for comparison.
355 // following the load, which will be done by the SUBREG_TO_REG
383 // a SUBREG_TO_REG, which is handled by introducing a swap.
388 case PPC::SUBREG_TO_REG: {
853 DEBUG(dbgs() << "Changing SUBREG_TO_REG: ");
866 // Note that an XXPERMDI requires a VSRC, so if the SUBREG_TO_REG
[all...] |
| /external/llvm/lib/CodeGen/ |
| ExpandPostRAPseudos.cpp | 10 // This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
85 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
111 // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
211 case TargetOpcode::SUBREG_TO_REG:
|
| PeepholeOptimizer.cpp | 473 // %reg1026 = SUBREG_TO_REG 0, %reg1024, 4
480 // %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
482 // The problem here is that SUBREG_TO_REG is there to assert that an
486 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 777 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
818 case TargetOpcode::SUBREG_TO_REG:
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ResourcePriorityQueue.cpp | 265 case TargetOpcode::SUBREG_TO_REG:
305 case TargetOpcode::SUBREG_TO_REG:
|
| InstrEmitter.cpp | 528 Opc == TargetOpcode::SUBREG_TO_REG) {
555 // Create the insert_subreg or subreg_to_reg machine instruction.
559 // If creating a subreg_to_reg, then the first input operand
561 if (Opc == TargetOpcode::SUBREG_TO_REG) {
573 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
728 Opc == TargetOpcode::SUBREG_TO_REG) {
[all...] |
| ScheduleDAGRRList.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.cpp | 55 case TargetOpcode::SUBREG_TO_REG:
107 case TargetOpcode::SUBREG_TO_REG:
|
| HexagonInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | [all...] |
| AArch64ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 260 Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT,
[all...] |
| MipsSEISelLowering.cpp | [all...] |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| X86ISelDAGToDAG.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
