| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 98 unsigned Src1 = 0;
102 Src1 = MI.getOperand(2).getReg();
107 Src1 = TRI.getSubReg(Src1, SubRegIndex);
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
153 .addReg(Src1)
|
| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| Execution.cpp | 52 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
55 static void executeFAddInst(GenericValue &Dest, GenericValue Src1,
66 static void executeFSubInst(GenericValue &Dest, GenericValue Src1,
77 static void executeFMulInst(GenericValue &Dest, GenericValue Src1,
88 static void executeFDivInst(GenericValue &Dest, GenericValue Src1,
99 static void executeFRemInst(GenericValue &Dest, GenericValue Src1,
103 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal);
106 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal);
116 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
121 assert(Src1.AggregateVal.size() == Src2.AggregateVal.size());
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 215 unsigned Src1 = 0, SubReg1;
233 Src1 = getSrcFromCopy(&*Def, MRI, SubReg1);
234 if (Src1)
238 if (Src1 && MRI->hasOneNonDBGUse(OrigSrc1))
308 unsigned Src1 = 0, SubReg1;
326 Src1 = getSrcFromCopy(&*Def, MRI, SubReg1);
329 if (Src1 && MRI->hasOneNonDBGUse(OrigSrc1)) {
330 assert(Src1 && "Can't delete copy w/o a valid original source!");
342 if (!Src1) {
344 Src1 = MRI->createVirtualRegister(&AArch64::FPR64RegClass)
[all...] |
| AArch64FastISel.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ExpandSpecialInstrs.cpp | 109 AMDGPU::ZERO); // src1
225 unsigned Src1 = BMI->getOperand(
226 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1))
229 (void) Src1;
231 (TRI.getEncodingValue(Src1) & 0xff) < 127)
232 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
276 unsigned Src1 = 0;
280 int Src1Idx = TII->getOperandIdx(MI, AMDGPU::OpName::src1);
282 Src1 = MI.getOperand(Src1Idx).getReg();
288 Src1 = TRI.getSubReg(Src1, SubRegIndex)
[all...] |
| SIShrinkInstructions.cpp | 112 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
116 if (Src1 && (!isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->getImm() != 0)))
304 const MachineOperand *Src1 =
305 TII->getNamedOperand(MI, AMDGPU::OpName::src1);
306 if (Src1)
307 Inst32.addOperand(*Src1);
|
| SIInstrInfo.cpp | 835 unsigned Src1 = MI->getOperand(2).getReg();
840 .addReg(RI.getSubReg(Src1, AMDGPU::sub0))
844 .addReg(RI.getSubReg(Src1, AMDGPU::sub1))
903 AMDGPU::OpName::src1);
911 MachineOperand &Src1 = MI->getOperand(Src1Idx);
917 // sure we can use the src1 as src0.
927 if (!Src1.isReg()) {
929 if (NewMI || !Src1.isImm() ||
954 if (Src1.isImm())
955 Src0.ChangeToImmediate(Src1.getImm())
[all...] |
| R600InstrInfo.cpp | 261 AMDGPU::OpName::src1,
272 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
325 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
553 //Todo : support shared src0 - src1 operand
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonGenMux.cpp | 92 unsigned getMuxOpcode(const MachineOperand &Src1,
171 unsigned HexagonGenMux::getMuxOpcode(const MachineOperand &Src1,
173 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg();
262 MachineOperand *Src1 = &Def1->getOperand(2), *Src2 = &Def2->getOperand(2);
263 unsigned SR1 = Src1->isReg() ? Src1->getReg() : 0;
280 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2;
281 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2;
|
| HexagonPeephole.cpp | 159 MachineOperand &Src1 = MI->getOperand(1);
161 if (Src1.getImm() != 0)
176 MachineOperand &Src1 = MI->getOperand(1);
181 unsigned SrcReg = Src1.getReg();
|
| HexagonISelDAGToDAG.cpp | 557 // : STInst<(outs), (ins IntRegs:$base, imm:$offset, DoubleRegs:$src1), ...
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZSelectionDAGInfo.h | 41 SDValue Src1, SDValue Src2, SDValue Size,
59 SDValue Src1, SDValue Src2,
|
| SystemZSelectionDAGInfo.cpp | 151 // Use CLC to compare [Src1, Src1 + Size) with [Src2, Src2 + Size),
154 SDValue Src1, SDValue Src2, uint64_t Size) {
156 EVT PtrVT = Src1.getValueType();
166 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2,
169 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2,
188 SDValue Src1, SDValue Src2, SDValue Size,
194 Chain = emitCLC(DAG, DL, Chain, Src1, Src2, Bytes);
242 SDValue Src1, SDValue Src2,
245 SDVTList VTs = DAG.getVTList(Src1.getValueType(), MVT::Other, MVT::Glue)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FixupLEAs.cpp | 147 // if src1 != src2, then convertToThreeAddress will
369 const MachineOperand &Src1 = MI->getOperand(SrcR1 == DstR ? 1 : 3);
373 .addOperand(Src1)
|
| X86ISelLowering.cpp | [all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/api/ |
| armCOMM_IDCT_s.h | 672 Src1 EQU 8
682 qXj1 QN Src1.S16
693 dXj1lo DN (Src1*2).S16
694 dXj1hi DN (Src1*2+1).S16
885 XTR6 EQU Src1
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/api/ |
| armCOMM_IDCT_s.h | 678 Src1 EQU 8
688 qXj1 QN Src1.S16
699 dXj1lo DN (Src1*2).S16
700 dXj1hi DN (Src1*2+1).S16
891 XTR6 EQU Src1
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | [all...] |
| LegalizeVectorTypes.cpp | [all...] |
| /external/clang/lib/CodeGen/ |
| CGBuiltin.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
