| /external/llvm/include/llvm/CodeGen/ |
| LivePhysRegs.h | 77 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
78 SubRegs.isValid(); ++SubRegs)
79 LiveRegs.insert(*SubRegs);
87 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
88 SubRegs.isValid(); ++SubRegs)
89 LiveRegs.erase(*SubRegs);
|
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPURegisterInfo.cpp | 46 static const unsigned SubRegs[] = {
53 assert(Channel < array_lengthof(SubRegs));
54 return SubRegs[Channel];
|
| /external/llvm/lib/CodeGen/ |
| LiveVariables.cpp | 197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
198 unsigned SubReg = *SubRegs;
220 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true);
221 SubRegs.isValid(); ++SubRegs)
222 PartDefRegs.insert(*SubRegs);
251 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
[all...] |
| MachineVerifier.cpp | 94 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
95 RV.push_back(*SubRegs);
475 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
477 // assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register");
478 regsReserved.set(*SubRegs);
699 for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true)
[all...] |
| CriticalAntiDepBreaker.cpp | 217 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
218 SubRegs.isValid(); ++SubRegs) {
219 KeepRegs.set(*SubRegs);
229 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
230 SubRegs.isValid(); ++SubRegs)
231 KeepRegs.set(*SubRegs);
271 // For the reg itself and all subregs: update the def to current;
|
| MachineInstrBundle.cpp | 186 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
187 unsigned SubReg = *SubRegs;
|
| ScheduleDAGInstrs.cpp | [all...] |
| RegisterScavenging.cpp | 217 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
218 if (isRegUsed(*SubRegs)) {
|
| AggressiveAntiDepBreaker.cpp | 244 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
245 SubRegs.isValid(); ++SubRegs)
246 PassthruRegs.insert(*SubRegs);
318 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
319 unsigned SubregReg = *SubRegs;
[all...] |
| BranchFolding.cpp | 157 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
158 SubRegs.isValid(); ++SubRegs)
159 ImpDefRegs.insert(*SubRegs);
[all...] |
| IfConversion.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 119 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
123 "SubRegs and SubRegIndices must have the same size");
131 // covered-by-subregs super-registers where it appears as the first explicit
204 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
218 return SubRegs;
223 // First insert the explicit subregs and make sure they are fully indexed.
227 if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
235 // Keep track of inherited subregs and how they can be reached.
238 // Clone inherited subregs and place duplicate entries in Orphans
[all...] |
| CodeGenRegisters.h | 159 return SubRegs;
252 SubRegMap SubRegs;
|
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 99 /// register. The SubRegs field is a zero terminated array of registers that
107 uint32_t SubRegs; // Sub-register set, described above
111 // sub-register in SubRegs.
458 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 201 for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) {
203 if (*SubRegs > RegNo)
204 RegNo = *SubRegs;
206 if (!RegNo || *SubRegs < RegNo)
207 RegNo = *SubRegs;
688 // Split the double regs into subregs, and generate appropriate
[all...] |
| HexagonCopyToCombine.cpp | 389 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
390 LastDef[*SubRegs] = MI;
|
| HexagonInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 741 unsigned SubRegs = 0;
748 SubRegs = 2;
752 SubRegs = 4;
757 SubRegs = 2;
761 SubRegs = 3;
765 SubRegs = 4;
769 SubRegs = 2;
773 SubRegs = 2;
778 SubRegs = 3;
783 SubRegs = 4
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 148 const unsigned SubRegs[]);
[all...] |
