| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 352 /// At first, the VSELECT condition is of vXi1 type. Later, targets may
353 /// change the condition type in order to match the VSELECT node using a
355 VSELECT,
[all...] |
| BasicTTIImpl.h | 445 ISD = ISD::VSELECT;
|
| SelectionDAG.h | 746 return getNode(Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT, DL, VT,
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| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 80 setTargetDAGCombine(ISD::VSELECT);
98 setTargetDAGCombine(ISD::VSELECT);
275 setOperationAction(ISD::VSELECT, Ty, Legal);
320 setOperationAction(ISD::VSELECT, Ty, Legal);
660 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
776 // Transform the DAG into an equivalent VSELECT.
777 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 101 /// \brief Implement vselect in terms of XOR, AND, OR when blend is not
291 case ISD::VSELECT:
710 case ISD::VSELECT:
729 // operands are vectors. Lower this select to VSELECT and implement it
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| LegalizeVectorTypes.cpp | 63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
452 case ISD::VSELECT:
593 case ISD::VSELECT:
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| SelectionDAGDumper.cpp | 215 case ISD::VSELECT: return "vselect";
|
| LegalizeIntegerTypes.cpp | 75 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
577 return DAG.getNode(ISD::VSELECT, SDLoc(N),
[all...] |
| SelectionDAGBuilder.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 485 setOperationAction(ISD::VSELECT, VT, Expand);
586 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
587 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
588 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
589 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
590 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
676 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
726 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
[all...] |
| PPCISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 324 setOperationAction(ISD::VSELECT, VT, Expand);
363 setOperationAction(ISD::VSELECT, VT, Expand);
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| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 502 setTargetDAGCombine(ISD::VSELECT);
677 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
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| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 286 setOperationAction(ISD::VSELECT, VT, Legal);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 120 setOperationAction(ISD::VSELECT, VT, Expand);
[all...] |
