| /external/v8/src/x64/ |
| codegen-x64.h | 40 Register base_reg,
45 : base_reg_(base_reg),
53 Register base_reg,
58 : base_reg_(base_reg),
66 Register base_reg,
71 : base_reg_(base_reg),
|
| disasm-x64.cc | 346 int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); } function in class:disasm::DisassemblerX64
[all...] |
| code-stubs-x64.cc | 5000 Register base_reg = r15; local
[all...] |
| assembler-x64.cc | 214 int base_reg = (has_sib ? operand.buf_[1] : modrm) & 0x07;
217 bool is_baseless = (mode == 0) && (base_reg == 0x05); // No base or RIP base.
237 } else if (disp_value != 0 || (base_reg == 0x05)) {
[all...] |
| /external/mesa3d/src/mesa/program/ |
| register_allocate.h | 44 unsigned int base_reg, unsigned int reg);
|
| register_allocate.c | 210 * Adds a conflict between base_reg and reg, and also between reg and
211 * anything that base_reg conflicts with.
219 unsigned int base_reg, unsigned int reg)
223 ra_add_reg_conflict(regs, reg, base_reg);
225 for (i = 0; i < regs->regs[base_reg].num_conflicts; i++) {
226 ra_add_reg_conflict(regs, reg, regs->regs[base_reg].conflict_list[i]);
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| metag-dis.c | 472 const char *base_reg; local
481 base_reg = lookup_reg_name (base_unit, base_no);
491 snprintf (buf, buf_size, "[%s]", base_reg);
498 snprintf (buf, buf_size, "[%s++]", base_reg);
500 snprintf (buf, buf_size, "[++%s]", base_reg);
507 snprintf (buf, buf_size, "[%s--]", base_reg);
509 snprintf (buf, buf_size, "[--%s]", base_reg);
519 snprintf (buf, buf_size, "[%s+#%d++]", base_reg, offset);
521 snprintf (buf, buf_size, "[%s++#%d]", base_reg, offset);
524 snprintf (buf, buf_size, "[%s+#%d]", base_reg, offset)
552 const char *base_reg; local
582 const char *base_reg; local
598 const char *base_reg; local
614 const char *base_reg; local
909 const char *base_reg; local
2330 const char *base_reg = "?"; local
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vec4_reg_allocate.cpp | 131 for (int base_reg = j;
132 base_reg < j + class_sizes[i];
133 base_reg++) {
134 ra_add_transitive_reg_conflict(brw->vs.regs, base_reg, reg);
|
| brw_fs_reg_allocate.cpp | 119 for (int base_reg = j;
120 base_reg < j + class_sizes[i];
121 base_reg++) {
122 ra_add_transitive_reg_conflict(brw->wm.regs, base_reg, reg);
|
| brw_blorp_blit.cpp | 493 void alloc_push_const_regs(int base_reg);
743 brw_blorp_blit_program::alloc_push_const_regs(int base_reg)
748 brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 2)
[all...] |
| brw_wm_emit.c | [all...] |
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-metag.c | 186 const metag_reg *base_reg; member in struct:__anon75203
736 if (regs[0]->unit != addr->base_reg->unit)
768 addr->base_reg = regs[0];
1063 (regs[0]->unit == addr.base_reg->unit ||
1064 (size == 8 && is_unit_pair (regs[0], addr.base_reg))))
1087 if (!is_short_unit (addr.base_reg->unit))
1093 insn->bits |= ((addr.base_reg->no << 14) |
1094 ((addr.base_reg->unit & SHORT_UNIT_MASK) << 5));
1188 if (!is_short_unit (addr.base_reg->unit))
1194 if (addr.base_reg->no > 1
[all...] |
| tc-i386.c | 311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
313 const reg_entry *base_reg; member in struct:_i386_insn
[all...] |
| tc-tic6x.c | 1143 tic6x_register base_reg; member in struct:__anon75263
1425 tic6x_register base_reg; local
[all...] |
| tc-i386-intel.c | 970 i.base_reg = intel_state.index;
975 i.base_reg = intel_state.base;
|
| tc-arm.c | 1748 int base_reg; local
1893 mask >>= base_reg; local
1951 int base_reg = -1; local
8501 int base_reg = inst.operands[0].reg; local
[all...] |
| tc-ia64.c | 4618 int ch, base_reg = 0; local
[all...] |
| /external/v8/test/unittests/compiler/ia32/ |
| instruction-selector-ia32-unittest.cc | 344 Node* base_reg; // opaque value to generate base as register member in class:v8::internal::compiler::AddressingModeUnitTest
356 base_reg = m->Parameter(0);
368 Node* base = base_reg;
375 Node* base = base_reg;
382 Node* base = base_reg;
392 Node* base = base_reg;
401 Node* base = base_reg;
412 Node* base = base_reg;
|
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_state_init.c | 423 uint32_t base_reg; local
435 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break;
436 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break;
438 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break;
444 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));
[all...] |
| /art/compiler/utils/arm/ |
| assembler_arm32.h | 317 JumpTable* CreateJumpTable(std::vector<Label*>&& labels, Register base_reg) OVERRIDE;
|
| assembler_thumb2.h | 373 // Emit an ADR (or a sequence of instructions) to load the jump table address into base_reg. This
375 JumpTable* CreateJumpTable(std::vector<Label*>&& labels, Register base_reg) OVERRIDE;
[all...] |
| assembler_thumb2.cc | [all...] |
| assembler_arm.h | [all...] |
| /art/compiler/optimizing/ |
| code_generator_arm.cc | 5267 Register base_reg = locations->InAt(0).AsRegister<Register>(); local
6355 Register base_reg = GetInvokeStaticOrDirectExtraParameter(invoke, local
[all...] |
| code_generator_x86.cc | 4357 Register base_reg = GetInvokeStaticOrDirectExtraParameter(invoke, local
6054 Register base_reg = locations->InAt(0).AsRegister<Register>(); local
[all...] |
