| /art/runtime/interpreter/mterp/mips64/ |
| fcmp.S | 16 bc1nez f2, 1f # done if vBB == vCC (ordered)
20 bc1nez f2, 1f # done if vBB < vCC (ordered)
25 bc1nez f2, 1f # done if vBB > vCC (ordered)
|
| fcmpWide.S | 16 bc1nez f2, 1f # done if vBB == vCC (ordered)
20 bc1nez f2, 1f # done if vBB < vCC (ordered)
25 bc1nez f2, 1f # done if vBB > vCC (ordered)
|
| op_double_to_int.S | 9 bc1nez f1, .L${opcode}_trunc
|
| op_double_to_long.S | 9 bc1nez f1, .L${opcode}_trunc
|
| op_float_to_int.S | 9 bc1nez f1, .L${opcode}_trunc
|
| op_float_to_long.S | 9 bc1nez f1, .L${opcode}_trunc
|
| /art/runtime/interpreter/mterp/mips/ |
| op_cmpl_double.S | 25 bc1nez ft2, .L${opcode}_finish
28 bc1nez ft2, .L${opcode}_finish
31 bc1nez ft2, .L${opcode}_finish
|
| op_cmpl_float.S | 32 bc1nez ft2, .L${opcode}_finish
35 bc1nez ft2, .L${opcode}_finish
38 bc1nez ft2, .L${opcode}_finish
|
| op_double_to_int.S | 17 bc1nez ft2, .L${opcode}_set_vreg_f
23 bc1nez ft2, .L${opcode}_set_vreg_f
28 bc1nez ft2, .L${opcode}_set_vreg_f
|
| op_double_to_long.S | 11 bc1nez ft2, .L${opcode}_set_vreg
18 bc1nez ft2, .L${opcode}_set_vreg
24 bc1nez ft2, .L${opcode}_set_vreg
|
| op_float_to_int.S | 12 bc1nez ft2, .L${opcode}_set_vreg_f
17 bc1nez ft2, .L${opcode}_set_vreg_f
22 bc1nez ft2, .L${opcode}_set_vreg_f
|
| op_float_to_long.S | 10 bc1nez ft2, .L${opcode}_set_vreg
16 bc1nez ft2, .L${opcode}_set_vreg
22 bc1nez ft2, .L${opcode}_set_vreg
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| r6.s | 55 bc1nez $f0,1f
56 bc1nez $f31,1f
57 bc1nez $f31,new
58 bc1nez $f31,external_label
|
| r6-n32.d | 71 0+00e0 <[^>]*> 45a00000 bc1nez \$f0,000000e4 <[^>]*>
74 0+00e8 <[^>]*> 45bf0000 bc1nez \$f31,000000ec <[^>]*>
77 0+00f0 <[^>]*> 45bf0000 bc1nez \$f31,000000f4 <[^>]*>
80 0+00f8 <[^>]*> 45bf0000 bc1nez \$f31,000000fc <[^>]*>
|
| r6.d | 70 0+00e0 <[^>]*> 45a0ffff bc1nez \$f0,000000e0 <[^>]*>
73 0+00e8 <[^>]*> 45bfffff bc1nez \$f31,000000e8 <[^>]*>
76 0+00f0 <[^>]*> 45bfffff bc1nez \$f31,000000f0 <[^>]*>
79 0+00f8 <[^>]*> 45bfffff bc1nez \$f31,000000f8 <[^>]*>
|
| r6-n64.d | 79 0+00e0 <[^>]*> 45a00000 bc1nez \$f0,0+00e4 <[^>]*>
84 0+00e8 <[^>]*> 45bf0000 bc1nez \$f31,0+00ec <[^>]*>
89 0+00f0 <[^>]*> 45bf0000 bc1nez \$f31,0+00f4 <[^>]*>
94 0+00f8 <[^>]*> 45bf0000 bc1nez \$f31,0+00fc <[^>]*>
|
| /external/v8/test/cctest/ |
| test-disasm-mips.cc | 412 COMPARE_PC_REL_COMPACT(bc1nez(-32768, f1),
413 "45a18000 bc1nez f1, -32768", -32768);
414 COMPARE_PC_REL_COMPACT(bc1nez(-1, f1), "45a1ffff bc1nez f1, -1",
416 COMPARE_PC_REL_COMPACT(bc1nez(1, f1), "45a10001 bc1nez f1, 1", 1);
417 COMPARE_PC_REL_COMPACT(bc1nez(32767, f1),
418 "45a17fff bc1nez f1, 32767", 32767);
[all...] |
| test-disasm-mips64.cc | [all...] |
| /external/v8/src/mips/ |
| assembler-mips.h | [all...] |
| macro-assembler-mips.cc | [all...] |
| /external/v8/src/mips64/ |
| assembler-mips64.h | [all...] |
| disasm-mips64.cc | [all...] |
| /art/runtime/interpreter/mterp/out/ |
| mterp_mips.S | [all...] |
| mterp_mips64.S | [all...] |
| /external/llvm/test/MC/Mips/ |
| target-soft-float.s | 63 bc1nez $f2, 456
|
