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      1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file provides Mips specific target descriptions.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "InstPrinter/MipsInstPrinter.h"
     15 #include "MipsELFStreamer.h"
     16 #include "MipsMCAsmInfo.h"
     17 #include "MipsMCNaCl.h"
     18 #include "MipsMCTargetDesc.h"
     19 #include "MipsTargetStreamer.h"
     20 #include "llvm/ADT/Triple.h"
     21 #include "llvm/MC/MCCodeGenInfo.h"
     22 #include "llvm/MC/MCELFStreamer.h"
     23 #include "llvm/MC/MCInstrInfo.h"
     24 #include "llvm/MC/MCRegisterInfo.h"
     25 #include "llvm/MC/MCSubtargetInfo.h"
     26 #include "llvm/MC/MCSymbol.h"
     27 #include "llvm/MC/MachineLocation.h"
     28 #include "llvm/Support/CommandLine.h"
     29 #include "llvm/Support/ErrorHandling.h"
     30 #include "llvm/Support/FormattedStream.h"
     31 #include "llvm/Support/TargetRegistry.h"
     32 
     33 using namespace llvm;
     34 
     35 #define GET_INSTRINFO_MC_DESC
     36 #include "MipsGenInstrInfo.inc"
     37 
     38 #define GET_SUBTARGETINFO_MC_DESC
     39 #include "MipsGenSubtargetInfo.inc"
     40 
     41 #define GET_REGINFO_MC_DESC
     42 #include "MipsGenRegisterInfo.inc"
     43 
     44 /// Select the Mips CPU for the given triple and cpu name.
     45 /// FIXME: Merge with the copy in MipsSubtarget.cpp
     46 StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
     47   if (CPU.empty() || CPU == "generic") {
     48     if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
     49       CPU = "mips32";
     50     else
     51       CPU = "mips64";
     52   }
     53   return CPU;
     54 }
     55 
     56 static MCInstrInfo *createMipsMCInstrInfo() {
     57   MCInstrInfo *X = new MCInstrInfo();
     58   InitMipsMCInstrInfo(X);
     59   return X;
     60 }
     61 
     62 static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
     63   MCRegisterInfo *X = new MCRegisterInfo();
     64   InitMipsMCRegisterInfo(X, Mips::RA);
     65   return X;
     66 }
     67 
     68 static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
     69                                                   StringRef CPU, StringRef FS) {
     70   CPU = MIPS_MC::selectMipsCPU(TT, CPU);
     71   return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
     72 }
     73 
     74 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
     75                                       const Triple &TT) {
     76   MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
     77 
     78   unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
     79   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
     80   MAI->addInitialFrameState(Inst);
     81 
     82   return MAI;
     83 }
     84 
     85 static MCCodeGenInfo *createMipsMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
     86                                               CodeModel::Model CM,
     87                                               CodeGenOpt::Level OL) {
     88   MCCodeGenInfo *X = new MCCodeGenInfo();
     89   if (CM == CodeModel::JITDefault)
     90     RM = Reloc::Static;
     91   else if (RM == Reloc::Default)
     92     RM = Reloc::PIC_;
     93   X->initMCCodeGenInfo(RM, CM, OL);
     94   return X;
     95 }
     96 
     97 static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
     98                                               unsigned SyntaxVariant,
     99                                               const MCAsmInfo &MAI,
    100                                               const MCInstrInfo &MII,
    101                                               const MCRegisterInfo &MRI) {
    102   return new MipsInstPrinter(MAI, MII, MRI);
    103 }
    104 
    105 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
    106                                     MCAsmBackend &MAB, raw_pwrite_stream &OS,
    107                                     MCCodeEmitter *Emitter, bool RelaxAll) {
    108   MCStreamer *S;
    109   if (!T.isOSNaCl())
    110     S = createMipsELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
    111   else
    112     S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
    113   return S;
    114 }
    115 
    116 static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S,
    117                                                      formatted_raw_ostream &OS,
    118                                                      MCInstPrinter *InstPrint,
    119                                                      bool isVerboseAsm) {
    120   return new MipsTargetAsmStreamer(S, OS);
    121 }
    122 
    123 static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) {
    124   return new MipsTargetStreamer(S);
    125 }
    126 
    127 static MCTargetStreamer *
    128 createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
    129   return new MipsTargetELFStreamer(S, STI);
    130 }
    131 
    132 extern "C" void LLVMInitializeMipsTargetMC() {
    133   for (Target *T : {&TheMipsTarget, &TheMipselTarget, &TheMips64Target,
    134                     &TheMips64elTarget}) {
    135     // Register the MC asm info.
    136     RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
    137 
    138     // Register the MC codegen info.
    139     TargetRegistry::RegisterMCCodeGenInfo(*T, createMipsMCCodeGenInfo);
    140 
    141     // Register the MC instruction info.
    142     TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo);
    143 
    144     // Register the MC register info.
    145     TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo);
    146 
    147     // Register the elf streamer.
    148     TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
    149 
    150     // Register the asm target streamer.
    151     TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer);
    152 
    153     TargetRegistry::RegisterNullTargetStreamer(*T,
    154                                                createMipsNullTargetStreamer);
    155 
    156     // Register the MC subtarget info.
    157     TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo);
    158 
    159     // Register the MCInstPrinter.
    160     TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter);
    161 
    162     TargetRegistry::RegisterObjectTargetStreamer(
    163         *T, createMipsObjectTargetStreamer);
    164   }
    165 
    166   // Register the MC Code Emitter
    167   for (Target *T : {&TheMipsTarget, &TheMips64Target})
    168     TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB);
    169 
    170   for (Target *T : {&TheMipselTarget, &TheMips64elTarget})
    171     TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL);
    172 
    173   // Register the asm backend.
    174   TargetRegistry::RegisterMCAsmBackend(TheMipsTarget,
    175                                        createMipsAsmBackendEB32);
    176   TargetRegistry::RegisterMCAsmBackend(TheMipselTarget,
    177                                        createMipsAsmBackendEL32);
    178   TargetRegistry::RegisterMCAsmBackend(TheMips64Target,
    179                                        createMipsAsmBackendEB64);
    180   TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget,
    181                                        createMipsAsmBackendEL64);
    182 
    183 }
    184