| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 579 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
582 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
618 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
621 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
660 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
663 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
704 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
707 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
752 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
756 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMInstrInfo.cpp | 41 NopInst.addOperand(MCOperand::createReg(0));
44 NopInst.addOperand(MCOperand::createReg(ARM::R0));
45 NopInst.addOperand(MCOperand::createReg(ARM::R0));
47 NopInst.addOperand(MCOperand::createReg(0));
48 NopInst.addOperand(MCOperand::createReg(0));
|
| Thumb1InstrInfo.cpp | 30 NopInst.addOperand(MCOperand::createReg(ARM::R8));
31 NopInst.addOperand(MCOperand::createReg(ARM::R8));
33 NopInst.addOperand(MCOperand::createReg(0));
|
| ARMAsmPrinter.cpp | [all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 184 mcInst.addOperand(MCOperand::createReg(llvmRegnum));
252 MCOperand baseReg = MCOperand::createReg(baseRegNo);
256 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]);
277 MCOperand baseReg = MCOperand::createReg(baseRegNo);
543 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4)));
546 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4)));
549 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4)));
552 mcInst.addOperand(MCOperand::createReg(X86::BND0 + (immediate >> 4)));
585 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]);
618 mcInst.addOperand(MCOperand::createReg(X86::x)); break
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCInstBuilder.h | 33 Inst.addOperand(MCOperand::createReg(Reg));
|
| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| SystemZDisassembler.cpp | 55 Inst.addOperand(MCOperand::createReg(RegNo));
232 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
242 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
253 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
255 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
265 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
267 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
277 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
289 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
291 Inst.addOperand(MCOperand::createReg(SystemZMC::VR128Regs[Index]))
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsTargetStreamer.cpp | 762 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
771 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
772 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
781 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
782 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
783 TmpInst.addOperand(MCOperand::createReg(RegNo));
822 Inst.addOperand(MCOperand::createReg(RegOrOffset));
823 Inst.addOperand(MCOperand::createReg(Mips::GP));
824 Inst.addOperand(MCOperand::createReg(Mips::ZERO));
828 Inst.addOperand(MCOperand::createReg(Mips::GP))
[all...] |
| MipsNaClELFStreamer.cpp | 97 MaskInst.addOperand(MCOperand::createReg(AddrReg));
98 MaskInst.addOperand(MCOperand::createReg(AddrReg));
99 MaskInst.addOperand(MCOperand::createReg(MaskReg));
|
| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 476 Inst.addOperand(MCOperand::createReg(Table[RegNo]));
578 Inst.addOperand(MCOperand::createReg(Register));
602 Inst.addOperand(MCOperand::createReg(Register));
620 Inst.addOperand(MCOperand::createReg(Register));
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFMCInstLower.cpp | 59 MCOp = MCOperand::createReg(MO.getReg());
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86Operand.h | 386 Inst.addOperand(MCOperand::createReg(getReg()));
417 Inst.addOperand(MCOperand::createReg(RegNo));
430 Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
432 Inst.addOperand(MCOperand::createReg(getMemIndexReg()));
434 Inst.addOperand(MCOperand::createReg(getMemSegReg()));
448 Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
449 Inst.addOperand(MCOperand::createReg(getMemSegReg()));
453 Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
463 Inst.addOperand(MCOperand::createReg(getMemSegReg()));
475 CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcMCInstLower.cpp | 77 return MCOperand::createReg(MO.getReg());
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyMCInstLower.cpp | 75 MCOp = MCOperand::createReg(WAReg);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 470 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
503 Adrp.addOperand(MCOperand::createReg(AArch64::X0));
509 Ldr.addOperand(MCOperand::createReg(AArch64::X1));
510 Ldr.addOperand(MCOperand::createReg(AArch64::X0));
517 Add.addOperand(MCOperand::createReg(AArch64::X0));
518 Add.addOperand(MCOperand::createReg(AArch64::X0));
532 Blr.addOperand(MCOperand::createReg(AArch64::X1));
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430MCInstLower.cpp | 127 MCOp = MCOperand::createReg(MO.getReg());
|
| /external/llvm/lib/Target/Sparc/Disassembler/ |
| SparcDisassembler.cpp | 140 Inst.addOperand(MCOperand::createReg(Reg));
151 Inst.addOperand(MCOperand::createReg(Reg));
163 Inst.addOperand(MCOperand::createReg(Reg));
175 Inst.addOperand(MCOperand::createReg(Reg));
190 Inst.addOperand(MCOperand::createReg(Reg));
199 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo]));
208 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo]));
217 Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo]));
232 Inst.addOperand(MCOperand::createReg(RegisterPair));
|
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 146 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
256 Inst.addOperand(MCOperand::createReg(Mem.Base));
258 Inst.addOperand(MCOperand::createReg(Mem.Index));
270 Inst.addOperand(MCOperand::createReg(getReg()));
284 Inst.addOperand(MCOperand::createReg(Mem.Base));
290 Inst.addOperand(MCOperand::createReg(Mem.Base));
292 Inst.addOperand(MCOperand::createReg(Mem.Index));
297 Inst.addOperand(MCOperand::createReg(Mem.Base));
567 Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZMCInstLower.cpp | 83 return MCOperand::createReg(MO.getReg());
|
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 414 return MCOperand::createReg(MO.getReg());
549 OutMI.addOperand(MCOperand::createReg(ReturnReg));
748 LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest
749 LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
751 LEA.addOperand(MCOperand::createReg(0)); // index
753 LEA.addOperand(MCOperand::createReg(0)); // seg
756 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
757 LEA.addOperand(MCOperand::createReg(X86::EBX)); // base
759 LEA.addOperand(MCOperand::createReg(0)); // index
761 LEA.addOperand(MCOperand::createReg(0)); // se
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreMCInstLower.cpp | 90 return MCOperand::createReg(MO.getReg());
|
| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| PPCDisassembler.cpp | 211 Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
334 Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
341 Inst.insert(Inst.begin(), MCOperand::createReg(GP0Regs[Base]));
346 Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
362 Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
364 Inst.insert(Inst.begin(), MCOperand::createReg(GP0Regs[Base]));
367 Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
378 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 403 TmpInst.addOperand(MCOperand::createReg(High));
404 TmpInst.addOperand(MCOperand::createReg(Low));
489 MappedInst.addOperand(MCOperand::createReg(Low));
501 MappedInst.addOperand(MCOperand::createReg(Low));
514 MappedInst.addOperand(MCOperand::createReg(Low));
|
| /external/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.cpp | 123 TmpInst0.addOperand(MCOperand::createReg(ZeroReg));
786 I.addOperand(MCOperand::createReg(Reg));
805 I.addOperand(MCOperand::createReg(Reg1));
806 I.addOperand(MCOperand::createReg(Reg2));
815 I.addOperand(MCOperand::createReg(Reg1));
816 I.addOperand(MCOperand::createReg(Reg2));
817 I.addOperand(MCOperand::createReg(Reg3));
[all...] |
