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      1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
     11 #include "llvm/ADT/STLExtras.h"
     12 #include "llvm/MC/MCContext.h"
     13 #include "llvm/MC/MCExpr.h"
     14 #include "llvm/MC/MCInst.h"
     15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
     16 #include "llvm/MC/MCStreamer.h"
     17 #include "llvm/MC/MCSubtargetInfo.h"
     18 #include "llvm/MC/MCTargetAsmParser.h"
     19 #include "llvm/Support/TargetRegistry.h"
     20 
     21 using namespace llvm;
     22 
     23 // Return true if Expr is in the range [MinValue, MaxValue].
     24 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
     25   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
     26     int64_t Value = CE->getValue();
     27     return Value >= MinValue && Value <= MaxValue;
     28   }
     29   return false;
     30 }
     31 
     32 namespace {
     33 enum RegisterKind {
     34   GR32Reg,
     35   GRH32Reg,
     36   GR64Reg,
     37   GR128Reg,
     38   ADDR32Reg,
     39   ADDR64Reg,
     40   FP32Reg,
     41   FP64Reg,
     42   FP128Reg,
     43   VR32Reg,
     44   VR64Reg,
     45   VR128Reg
     46 };
     47 
     48 enum MemoryKind {
     49   BDMem,
     50   BDXMem,
     51   BDLMem,
     52   BDVMem
     53 };
     54 
     55 class SystemZOperand : public MCParsedAsmOperand {
     56 public:
     57 private:
     58   enum OperandKind {
     59     KindInvalid,
     60     KindToken,
     61     KindReg,
     62     KindAccessReg,
     63     KindImm,
     64     KindImmTLS,
     65     KindMem
     66   };
     67 
     68   OperandKind Kind;
     69   SMLoc StartLoc, EndLoc;
     70 
     71   // A string of length Length, starting at Data.
     72   struct TokenOp {
     73     const char *Data;
     74     unsigned Length;
     75   };
     76 
     77   // LLVM register Num, which has kind Kind.  In some ways it might be
     78   // easier for this class to have a register bank (general, floating-point
     79   // or access) and a raw register number (0-15).  This would postpone the
     80   // interpretation of the operand to the add*() methods and avoid the need
     81   // for context-dependent parsing.  However, we do things the current way
     82   // because of the virtual getReg() method, which needs to distinguish
     83   // between (say) %r0 used as a single register and %r0 used as a pair.
     84   // Context-dependent parsing can also give us slightly better error
     85   // messages when invalid pairs like %r1 are used.
     86   struct RegOp {
     87     RegisterKind Kind;
     88     unsigned Num;
     89   };
     90 
     91   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
     92   // MemKind says what type of memory this is and RegKind says what type
     93   // the base register has (ADDR32Reg or ADDR64Reg).  Length is the operand
     94   // length for D(L,B)-style operands, otherwise it is null.
     95   struct MemOp {
     96     unsigned Base : 12;
     97     unsigned Index : 12;
     98     unsigned MemKind : 4;
     99     unsigned RegKind : 4;
    100     const MCExpr *Disp;
    101     const MCExpr *Length;
    102   };
    103 
    104   // Imm is an immediate operand, and Sym is an optional TLS symbol
    105   // for use with a __tls_get_offset marker relocation.
    106   struct ImmTLSOp {
    107     const MCExpr *Imm;
    108     const MCExpr *Sym;
    109   };
    110 
    111   union {
    112     TokenOp Token;
    113     RegOp Reg;
    114     unsigned AccessReg;
    115     const MCExpr *Imm;
    116     ImmTLSOp ImmTLS;
    117     MemOp Mem;
    118   };
    119 
    120   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
    121     // Add as immediates when possible.  Null MCExpr = 0.
    122     if (!Expr)
    123       Inst.addOperand(MCOperand::createImm(0));
    124     else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
    125       Inst.addOperand(MCOperand::createImm(CE->getValue()));
    126     else
    127       Inst.addOperand(MCOperand::createExpr(Expr));
    128   }
    129 
    130 public:
    131   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
    132       : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
    133 
    134   // Create particular kinds of operand.
    135   static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
    136                                                        SMLoc EndLoc) {
    137     return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
    138   }
    139   static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
    140     auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
    141     Op->Token.Data = Str.data();
    142     Op->Token.Length = Str.size();
    143     return Op;
    144   }
    145   static std::unique_ptr<SystemZOperand>
    146   createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
    147     auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
    148     Op->Reg.Kind = Kind;
    149     Op->Reg.Num = Num;
    150     return Op;
    151   }
    152   static std::unique_ptr<SystemZOperand>
    153   createAccessReg(unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
    154     auto Op = make_unique<SystemZOperand>(KindAccessReg, StartLoc, EndLoc);
    155     Op->AccessReg = Num;
    156     return Op;
    157   }
    158   static std::unique_ptr<SystemZOperand>
    159   createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
    160     auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
    161     Op->Imm = Expr;
    162     return Op;
    163   }
    164   static std::unique_ptr<SystemZOperand>
    165   createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
    166             const MCExpr *Disp, unsigned Index, const MCExpr *Length,
    167             SMLoc StartLoc, SMLoc EndLoc) {
    168     auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
    169     Op->Mem.MemKind = MemKind;
    170     Op->Mem.RegKind = RegKind;
    171     Op->Mem.Base = Base;
    172     Op->Mem.Index = Index;
    173     Op->Mem.Disp = Disp;
    174     Op->Mem.Length = Length;
    175     return Op;
    176   }
    177   static std::unique_ptr<SystemZOperand>
    178   createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
    179                SMLoc StartLoc, SMLoc EndLoc) {
    180     auto Op = make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
    181     Op->ImmTLS.Imm = Imm;
    182     Op->ImmTLS.Sym = Sym;
    183     return Op;
    184   }
    185 
    186   // Token operands
    187   bool isToken() const override {
    188     return Kind == KindToken;
    189   }
    190   StringRef getToken() const {
    191     assert(Kind == KindToken && "Not a token");
    192     return StringRef(Token.Data, Token.Length);
    193   }
    194 
    195   // Register operands.
    196   bool isReg() const override {
    197     return Kind == KindReg;
    198   }
    199   bool isReg(RegisterKind RegKind) const {
    200     return Kind == KindReg && Reg.Kind == RegKind;
    201   }
    202   unsigned getReg() const override {
    203     assert(Kind == KindReg && "Not a register");
    204     return Reg.Num;
    205   }
    206 
    207   // Access register operands.  Access registers aren't exposed to LLVM
    208   // as registers.
    209   bool isAccessReg() const {
    210     return Kind == KindAccessReg;
    211   }
    212 
    213   // Immediate operands.
    214   bool isImm() const override {
    215     return Kind == KindImm;
    216   }
    217   bool isImm(int64_t MinValue, int64_t MaxValue) const {
    218     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
    219   }
    220   const MCExpr *getImm() const {
    221     assert(Kind == KindImm && "Not an immediate");
    222     return Imm;
    223   }
    224 
    225   // Immediate operands with optional TLS symbol.
    226   bool isImmTLS() const {
    227     return Kind == KindImmTLS;
    228   }
    229 
    230   // Memory operands.
    231   bool isMem() const override {
    232     return Kind == KindMem;
    233   }
    234   bool isMem(MemoryKind MemKind) const {
    235     return (Kind == KindMem &&
    236             (Mem.MemKind == MemKind ||
    237              // A BDMem can be treated as a BDXMem in which the index
    238              // register field is 0.
    239              (Mem.MemKind == BDMem && MemKind == BDXMem)));
    240   }
    241   bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
    242     return isMem(MemKind) && Mem.RegKind == RegKind;
    243   }
    244   bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
    245     return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
    246   }
    247   bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
    248     return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
    249   }
    250   bool isMemDisp12Len8(RegisterKind RegKind) const {
    251     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length, 1, 0x100);
    252   }
    253   void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
    254     assert(N == 3 && "Invalid number of operands");
    255     assert(isMem(BDVMem) && "Invalid operand type");
    256     Inst.addOperand(MCOperand::createReg(Mem.Base));
    257     addExpr(Inst, Mem.Disp);
    258     Inst.addOperand(MCOperand::createReg(Mem.Index));
    259   }
    260 
    261   // Override MCParsedAsmOperand.
    262   SMLoc getStartLoc() const override { return StartLoc; }
    263   SMLoc getEndLoc() const override { return EndLoc; }
    264   void print(raw_ostream &OS) const override;
    265 
    266   // Used by the TableGen code to add particular types of operand
    267   // to an instruction.
    268   void addRegOperands(MCInst &Inst, unsigned N) const {
    269     assert(N == 1 && "Invalid number of operands");
    270     Inst.addOperand(MCOperand::createReg(getReg()));
    271   }
    272   void addAccessRegOperands(MCInst &Inst, unsigned N) const {
    273     assert(N == 1 && "Invalid number of operands");
    274     assert(Kind == KindAccessReg && "Invalid operand type");
    275     Inst.addOperand(MCOperand::createImm(AccessReg));
    276   }
    277   void addImmOperands(MCInst &Inst, unsigned N) const {
    278     assert(N == 1 && "Invalid number of operands");
    279     addExpr(Inst, getImm());
    280   }
    281   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
    282     assert(N == 2 && "Invalid number of operands");
    283     assert(isMem(BDMem) && "Invalid operand type");
    284     Inst.addOperand(MCOperand::createReg(Mem.Base));
    285     addExpr(Inst, Mem.Disp);
    286   }
    287   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
    288     assert(N == 3 && "Invalid number of operands");
    289     assert(isMem(BDXMem) && "Invalid operand type");
    290     Inst.addOperand(MCOperand::createReg(Mem.Base));
    291     addExpr(Inst, Mem.Disp);
    292     Inst.addOperand(MCOperand::createReg(Mem.Index));
    293   }
    294   void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
    295     assert(N == 3 && "Invalid number of operands");
    296     assert(isMem(BDLMem) && "Invalid operand type");
    297     Inst.addOperand(MCOperand::createReg(Mem.Base));
    298     addExpr(Inst, Mem.Disp);
    299     addExpr(Inst, Mem.Length);
    300   }
    301   void addImmTLSOperands(MCInst &Inst, unsigned N) const {
    302     assert(N == 2 && "Invalid number of operands");
    303     assert(Kind == KindImmTLS && "Invalid operand type");
    304     addExpr(Inst, ImmTLS.Imm);
    305     if (ImmTLS.Sym)
    306       addExpr(Inst, ImmTLS.Sym);
    307   }
    308 
    309   // Used by the TableGen code to check for particular operand types.
    310   bool isGR32() const { return isReg(GR32Reg); }
    311   bool isGRH32() const { return isReg(GRH32Reg); }
    312   bool isGRX32() const { return false; }
    313   bool isGR64() const { return isReg(GR64Reg); }
    314   bool isGR128() const { return isReg(GR128Reg); }
    315   bool isADDR32() const { return isReg(ADDR32Reg); }
    316   bool isADDR64() const { return isReg(ADDR64Reg); }
    317   bool isADDR128() const { return false; }
    318   bool isFP32() const { return isReg(FP32Reg); }
    319   bool isFP64() const { return isReg(FP64Reg); }
    320   bool isFP128() const { return isReg(FP128Reg); }
    321   bool isVR32() const { return isReg(VR32Reg); }
    322   bool isVR64() const { return isReg(VR64Reg); }
    323   bool isVF128() const { return false; }
    324   bool isVR128() const { return isReg(VR128Reg); }
    325   bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
    326   bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
    327   bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); }
    328   bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); }
    329   bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); }
    330   bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); }
    331   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
    332   bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); }
    333   bool isU1Imm() const { return isImm(0, 1); }
    334   bool isU2Imm() const { return isImm(0, 3); }
    335   bool isU3Imm() const { return isImm(0, 7); }
    336   bool isU4Imm() const { return isImm(0, 15); }
    337   bool isU6Imm() const { return isImm(0, 63); }
    338   bool isU8Imm() const { return isImm(0, 255); }
    339   bool isS8Imm() const { return isImm(-128, 127); }
    340   bool isU12Imm() const { return isImm(0, 4095); }
    341   bool isU16Imm() const { return isImm(0, 65535); }
    342   bool isS16Imm() const { return isImm(-32768, 32767); }
    343   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
    344   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
    345 };
    346 
    347 class SystemZAsmParser : public MCTargetAsmParser {
    348 #define GET_ASSEMBLER_HEADER
    349 #include "SystemZGenAsmMatcher.inc"
    350 
    351 private:
    352   MCAsmParser &Parser;
    353   enum RegisterGroup {
    354     RegGR,
    355     RegFP,
    356     RegV,
    357     RegAccess
    358   };
    359   struct Register {
    360     RegisterGroup Group;
    361     unsigned Num;
    362     SMLoc StartLoc, EndLoc;
    363   };
    364 
    365   bool parseRegister(Register &Reg);
    366 
    367   bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
    368                      bool IsAddress = false);
    369 
    370   OperandMatchResultTy parseRegister(OperandVector &Operands,
    371                                      RegisterGroup Group, const unsigned *Regs,
    372                                      RegisterKind Kind);
    373 
    374   bool parseAddress(unsigned &Base, const MCExpr *&Disp,
    375                     unsigned &Index, bool &IsVector, const MCExpr *&Length,
    376                     const unsigned *Regs, RegisterKind RegKind);
    377 
    378   OperandMatchResultTy parseAddress(OperandVector &Operands,
    379                                     MemoryKind MemKind, const unsigned *Regs,
    380                                     RegisterKind RegKind);
    381 
    382   OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
    383                                   int64_t MaxVal, bool AllowTLS);
    384 
    385   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
    386 
    387 public:
    388   SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
    389                    const MCInstrInfo &MII,
    390                    const MCTargetOptions &Options)
    391     : MCTargetAsmParser(Options, sti), Parser(parser) {
    392     MCAsmParserExtension::Initialize(Parser);
    393 
    394     // Initialize the set of available features.
    395     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
    396   }
    397 
    398   // Override MCTargetAsmParser.
    399   bool ParseDirective(AsmToken DirectiveID) override;
    400   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
    401   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
    402                         SMLoc NameLoc, OperandVector &Operands) override;
    403   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
    404                                OperandVector &Operands, MCStreamer &Out,
    405                                uint64_t &ErrorInfo,
    406                                bool MatchingInlineAsm) override;
    407 
    408   // Used by the TableGen code to parse particular operand types.
    409   OperandMatchResultTy parseGR32(OperandVector &Operands) {
    410     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
    411   }
    412   OperandMatchResultTy parseGRH32(OperandVector &Operands) {
    413     return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
    414   }
    415   OperandMatchResultTy parseGRX32(OperandVector &Operands) {
    416     llvm_unreachable("GRX32 should only be used for pseudo instructions");
    417   }
    418   OperandMatchResultTy parseGR64(OperandVector &Operands) {
    419     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
    420   }
    421   OperandMatchResultTy parseGR128(OperandVector &Operands) {
    422     return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
    423   }
    424   OperandMatchResultTy parseADDR32(OperandVector &Operands) {
    425     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
    426   }
    427   OperandMatchResultTy parseADDR64(OperandVector &Operands) {
    428     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
    429   }
    430   OperandMatchResultTy parseADDR128(OperandVector &Operands) {
    431     llvm_unreachable("Shouldn't be used as an operand");
    432   }
    433   OperandMatchResultTy parseFP32(OperandVector &Operands) {
    434     return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
    435   }
    436   OperandMatchResultTy parseFP64(OperandVector &Operands) {
    437     return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
    438   }
    439   OperandMatchResultTy parseFP128(OperandVector &Operands) {
    440     return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
    441   }
    442   OperandMatchResultTy parseVR32(OperandVector &Operands) {
    443     return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg);
    444   }
    445   OperandMatchResultTy parseVR64(OperandVector &Operands) {
    446     return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg);
    447   }
    448   OperandMatchResultTy parseVF128(OperandVector &Operands) {
    449     llvm_unreachable("Shouldn't be used as an operand");
    450   }
    451   OperandMatchResultTy parseVR128(OperandVector &Operands) {
    452     return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
    453   }
    454   OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
    455     return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
    456   }
    457   OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
    458     return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg);
    459   }
    460   OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
    461     return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg);
    462   }
    463   OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
    464     return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg);
    465   }
    466   OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
    467     return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
    468   }
    469   OperandMatchResultTy parseAccessReg(OperandVector &Operands);
    470   OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
    471     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
    472   }
    473   OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
    474     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
    475   }
    476   OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
    477     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
    478   }
    479   OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
    480     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
    481   }
    482 };
    483 } // end anonymous namespace
    484 
    485 #define GET_REGISTER_MATCHER
    486 #define GET_SUBTARGET_FEATURE_NAME
    487 #define GET_MATCHER_IMPLEMENTATION
    488 #include "SystemZGenAsmMatcher.inc"
    489 
    490 void SystemZOperand::print(raw_ostream &OS) const {
    491   llvm_unreachable("Not implemented");
    492 }
    493 
    494 // Parse one register of the form %<prefix><number>.
    495 bool SystemZAsmParser::parseRegister(Register &Reg) {
    496   Reg.StartLoc = Parser.getTok().getLoc();
    497 
    498   // Eat the % prefix.
    499   if (Parser.getTok().isNot(AsmToken::Percent))
    500     return Error(Parser.getTok().getLoc(), "register expected");
    501   Parser.Lex();
    502 
    503   // Expect a register name.
    504   if (Parser.getTok().isNot(AsmToken::Identifier))
    505     return Error(Reg.StartLoc, "invalid register");
    506 
    507   // Check that there's a prefix.
    508   StringRef Name = Parser.getTok().getString();
    509   if (Name.size() < 2)
    510     return Error(Reg.StartLoc, "invalid register");
    511   char Prefix = Name[0];
    512 
    513   // Treat the rest of the register name as a register number.
    514   if (Name.substr(1).getAsInteger(10, Reg.Num))
    515     return Error(Reg.StartLoc, "invalid register");
    516 
    517   // Look for valid combinations of prefix and number.
    518   if (Prefix == 'r' && Reg.Num < 16)
    519     Reg.Group = RegGR;
    520   else if (Prefix == 'f' && Reg.Num < 16)
    521     Reg.Group = RegFP;
    522   else if (Prefix == 'v' && Reg.Num < 32)
    523     Reg.Group = RegV;
    524   else if (Prefix == 'a' && Reg.Num < 16)
    525     Reg.Group = RegAccess;
    526   else
    527     return Error(Reg.StartLoc, "invalid register");
    528 
    529   Reg.EndLoc = Parser.getTok().getLoc();
    530   Parser.Lex();
    531   return false;
    532 }
    533 
    534 // Parse a register of group Group.  If Regs is nonnull, use it to map
    535 // the raw register number to LLVM numbering, with zero entries
    536 // indicating an invalid register.  IsAddress says whether the
    537 // register appears in an address context. Allow FP Group if expecting
    538 // RegV Group, since the f-prefix yields the FP group even while used
    539 // with vector instructions.
    540 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
    541                                      const unsigned *Regs, bool IsAddress) {
    542   if (parseRegister(Reg))
    543     return true;
    544   if (Reg.Group != Group && !(Reg.Group == RegFP && Group == RegV))
    545     return Error(Reg.StartLoc, "invalid operand for instruction");
    546   if (Regs && Regs[Reg.Num] == 0)
    547     return Error(Reg.StartLoc, "invalid register pair");
    548   if (Reg.Num == 0 && IsAddress)
    549     return Error(Reg.StartLoc, "%r0 used in an address");
    550   if (Regs)
    551     Reg.Num = Regs[Reg.Num];
    552   return false;
    553 }
    554 
    555 // Parse a register and add it to Operands.  The other arguments are as above.
    556 SystemZAsmParser::OperandMatchResultTy
    557 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
    558                                 const unsigned *Regs, RegisterKind Kind) {
    559   if (Parser.getTok().isNot(AsmToken::Percent))
    560     return MatchOperand_NoMatch;
    561 
    562   Register Reg;
    563   bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
    564   if (parseRegister(Reg, Group, Regs, IsAddress))
    565     return MatchOperand_ParseFail;
    566 
    567   Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
    568                                                Reg.StartLoc, Reg.EndLoc));
    569   return MatchOperand_Success;
    570 }
    571 
    572 // Parse a memory operand into Base, Disp, Index and Length.
    573 // Regs maps asm register numbers to LLVM register numbers and RegKind
    574 // says what kind of address register we're using (ADDR32Reg or ADDR64Reg).
    575 bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp,
    576                                     unsigned &Index, bool &IsVector,
    577                                     const MCExpr *&Length, const unsigned *Regs,
    578                                     RegisterKind RegKind) {
    579   // Parse the displacement, which must always be present.
    580   if (getParser().parseExpression(Disp))
    581     return true;
    582 
    583   // Parse the optional base and index.
    584   Index = 0;
    585   Base = 0;
    586   IsVector = false;
    587   Length = nullptr;
    588   if (getLexer().is(AsmToken::LParen)) {
    589     Parser.Lex();
    590 
    591     if (getLexer().is(AsmToken::Percent)) {
    592       // Parse the first register and decide whether it's a base or an index.
    593       Register Reg;
    594       if (parseRegister(Reg))
    595         return true;
    596       if (Reg.Group == RegV) {
    597         // A vector index register.  The base register is optional.
    598         IsVector = true;
    599         Index = SystemZMC::VR128Regs[Reg.Num];
    600       } else if (Reg.Group == RegGR) {
    601         if (Reg.Num == 0)
    602           return Error(Reg.StartLoc, "%r0 used in an address");
    603         // If the are two registers, the first one is the index and the
    604         // second is the base.
    605         if (getLexer().is(AsmToken::Comma))
    606           Index = Regs[Reg.Num];
    607         else
    608           Base = Regs[Reg.Num];
    609       } else
    610         return Error(Reg.StartLoc, "invalid address register");
    611     } else {
    612       // Parse the length.
    613       if (getParser().parseExpression(Length))
    614         return true;
    615     }
    616 
    617     // Check whether there's a second register.  It's the base if so.
    618     if (getLexer().is(AsmToken::Comma)) {
    619       Parser.Lex();
    620       Register Reg;
    621       if (parseRegister(Reg, RegGR, Regs, RegKind))
    622         return true;
    623       Base = Reg.Num;
    624     }
    625 
    626     // Consume the closing bracket.
    627     if (getLexer().isNot(AsmToken::RParen))
    628       return Error(Parser.getTok().getLoc(), "unexpected token in address");
    629     Parser.Lex();
    630   }
    631   return false;
    632 }
    633 
    634 // Parse a memory operand and add it to Operands.  The other arguments
    635 // are as above.
    636 SystemZAsmParser::OperandMatchResultTy
    637 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
    638                                const unsigned *Regs, RegisterKind RegKind) {
    639   SMLoc StartLoc = Parser.getTok().getLoc();
    640   unsigned Base, Index;
    641   bool IsVector;
    642   const MCExpr *Disp;
    643   const MCExpr *Length;
    644   if (parseAddress(Base, Disp, Index, IsVector, Length, Regs, RegKind))
    645     return MatchOperand_ParseFail;
    646 
    647   if (IsVector && MemKind != BDVMem) {
    648     Error(StartLoc, "invalid use of vector addressing");
    649     return MatchOperand_ParseFail;
    650   }
    651 
    652   if (!IsVector && MemKind == BDVMem) {
    653     Error(StartLoc, "vector index required in address");
    654     return MatchOperand_ParseFail;
    655   }
    656 
    657   if (Index && MemKind != BDXMem && MemKind != BDVMem) {
    658     Error(StartLoc, "invalid use of indexed addressing");
    659     return MatchOperand_ParseFail;
    660   }
    661 
    662   if (Length && MemKind != BDLMem) {
    663     Error(StartLoc, "invalid use of length addressing");
    664     return MatchOperand_ParseFail;
    665   }
    666 
    667   if (!Length && MemKind == BDLMem) {
    668     Error(StartLoc, "missing length in address");
    669     return MatchOperand_ParseFail;
    670   }
    671 
    672   SMLoc EndLoc =
    673     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
    674   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
    675                                                Index, Length, StartLoc,
    676                                                EndLoc));
    677   return MatchOperand_Success;
    678 }
    679 
    680 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
    681   return true;
    682 }
    683 
    684 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
    685                                      SMLoc &EndLoc) {
    686   Register Reg;
    687   if (parseRegister(Reg))
    688     return true;
    689   if (Reg.Group == RegGR)
    690     RegNo = SystemZMC::GR64Regs[Reg.Num];
    691   else if (Reg.Group == RegFP)
    692     RegNo = SystemZMC::FP64Regs[Reg.Num];
    693   else if (Reg.Group == RegV)
    694     RegNo = SystemZMC::VR128Regs[Reg.Num];
    695   else
    696     // FIXME: Access registers aren't modelled as LLVM registers yet.
    697     return Error(Reg.StartLoc, "invalid operand for instruction");
    698   StartLoc = Reg.StartLoc;
    699   EndLoc = Reg.EndLoc;
    700   return false;
    701 }
    702 
    703 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
    704                                         StringRef Name, SMLoc NameLoc,
    705                                         OperandVector &Operands) {
    706   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
    707 
    708   // Read the remaining operands.
    709   if (getLexer().isNot(AsmToken::EndOfStatement)) {
    710     // Read the first operand.
    711     if (parseOperand(Operands, Name)) {
    712       Parser.eatToEndOfStatement();
    713       return true;
    714     }
    715 
    716     // Read any subsequent operands.
    717     while (getLexer().is(AsmToken::Comma)) {
    718       Parser.Lex();
    719       if (parseOperand(Operands, Name)) {
    720         Parser.eatToEndOfStatement();
    721         return true;
    722       }
    723     }
    724     if (getLexer().isNot(AsmToken::EndOfStatement)) {
    725       SMLoc Loc = getLexer().getLoc();
    726       Parser.eatToEndOfStatement();
    727       return Error(Loc, "unexpected token in argument list");
    728     }
    729   }
    730 
    731   // Consume the EndOfStatement.
    732   Parser.Lex();
    733   return false;
    734 }
    735 
    736 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
    737                                     StringRef Mnemonic) {
    738   // Check if the current operand has a custom associated parser, if so, try to
    739   // custom parse the operand, or fallback to the general approach.
    740   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
    741   if (ResTy == MatchOperand_Success)
    742     return false;
    743 
    744   // If there wasn't a custom match, try the generic matcher below. Otherwise,
    745   // there was a match, but an error occurred, in which case, just return that
    746   // the operand parsing failed.
    747   if (ResTy == MatchOperand_ParseFail)
    748     return true;
    749 
    750   // Check for a register.  All real register operands should have used
    751   // a context-dependent parse routine, which gives the required register
    752   // class.  The code is here to mop up other cases, like those where
    753   // the instruction isn't recognized.
    754   if (Parser.getTok().is(AsmToken::Percent)) {
    755     Register Reg;
    756     if (parseRegister(Reg))
    757       return true;
    758     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
    759     return false;
    760   }
    761 
    762   // The only other type of operand is an immediate or address.  As above,
    763   // real address operands should have used a context-dependent parse routine,
    764   // so we treat any plain expression as an immediate.
    765   SMLoc StartLoc = Parser.getTok().getLoc();
    766   unsigned Base, Index;
    767   bool IsVector;
    768   const MCExpr *Expr, *Length;
    769   if (parseAddress(Base, Expr, Index, IsVector, Length, SystemZMC::GR64Regs,
    770                    ADDR64Reg))
    771     return true;
    772 
    773   SMLoc EndLoc =
    774     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
    775   if (Base || Index || Length)
    776     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
    777   else
    778     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
    779   return false;
    780 }
    781 
    782 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
    783                                                OperandVector &Operands,
    784                                                MCStreamer &Out,
    785                                                uint64_t &ErrorInfo,
    786                                                bool MatchingInlineAsm) {
    787   MCInst Inst;
    788   unsigned MatchResult;
    789 
    790   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
    791                                      MatchingInlineAsm);
    792   switch (MatchResult) {
    793   case Match_Success:
    794     Inst.setLoc(IDLoc);
    795     Out.EmitInstruction(Inst, getSTI());
    796     return false;
    797 
    798   case Match_MissingFeature: {
    799     assert(ErrorInfo && "Unknown missing feature!");
    800     // Special case the error message for the very common case where only
    801     // a single subtarget feature is missing
    802     std::string Msg = "instruction requires:";
    803     uint64_t Mask = 1;
    804     for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
    805       if (ErrorInfo & Mask) {
    806         Msg += " ";
    807         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
    808       }
    809       Mask <<= 1;
    810     }
    811     return Error(IDLoc, Msg);
    812   }
    813 
    814   case Match_InvalidOperand: {
    815     SMLoc ErrorLoc = IDLoc;
    816     if (ErrorInfo != ~0ULL) {
    817       if (ErrorInfo >= Operands.size())
    818         return Error(IDLoc, "too few operands for instruction");
    819 
    820       ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
    821       if (ErrorLoc == SMLoc())
    822         ErrorLoc = IDLoc;
    823     }
    824     return Error(ErrorLoc, "invalid operand for instruction");
    825   }
    826 
    827   case Match_MnemonicFail:
    828     return Error(IDLoc, "invalid instruction");
    829   }
    830 
    831   llvm_unreachable("Unexpected match type");
    832 }
    833 
    834 SystemZAsmParser::OperandMatchResultTy
    835 SystemZAsmParser::parseAccessReg(OperandVector &Operands) {
    836   if (Parser.getTok().isNot(AsmToken::Percent))
    837     return MatchOperand_NoMatch;
    838 
    839   Register Reg;
    840   if (parseRegister(Reg, RegAccess, nullptr))
    841     return MatchOperand_ParseFail;
    842 
    843   Operands.push_back(SystemZOperand::createAccessReg(Reg.Num,
    844                                                      Reg.StartLoc,
    845                                                      Reg.EndLoc));
    846   return MatchOperand_Success;
    847 }
    848 
    849 SystemZAsmParser::OperandMatchResultTy
    850 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
    851                              int64_t MaxVal, bool AllowTLS) {
    852   MCContext &Ctx = getContext();
    853   MCStreamer &Out = getStreamer();
    854   const MCExpr *Expr;
    855   SMLoc StartLoc = Parser.getTok().getLoc();
    856   if (getParser().parseExpression(Expr))
    857     return MatchOperand_NoMatch;
    858 
    859   // For consistency with the GNU assembler, treat immediates as offsets
    860   // from ".".
    861   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
    862     int64_t Value = CE->getValue();
    863     if ((Value & 1) || Value < MinVal || Value > MaxVal) {
    864       Error(StartLoc, "offset out of range");
    865       return MatchOperand_ParseFail;
    866     }
    867     MCSymbol *Sym = Ctx.createTempSymbol();
    868     Out.EmitLabel(Sym);
    869     const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
    870                                                  Ctx);
    871     Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
    872   }
    873 
    874   // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
    875   const MCExpr *Sym = nullptr;
    876   if (AllowTLS && getLexer().is(AsmToken::Colon)) {
    877     Parser.Lex();
    878 
    879     if (Parser.getTok().isNot(AsmToken::Identifier)) {
    880       Error(Parser.getTok().getLoc(), "unexpected token");
    881       return MatchOperand_ParseFail;
    882     }
    883 
    884     MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
    885     StringRef Name = Parser.getTok().getString();
    886     if (Name == "tls_gdcall")
    887       Kind = MCSymbolRefExpr::VK_TLSGD;
    888     else if (Name == "tls_ldcall")
    889       Kind = MCSymbolRefExpr::VK_TLSLDM;
    890     else {
    891       Error(Parser.getTok().getLoc(), "unknown TLS tag");
    892       return MatchOperand_ParseFail;
    893     }
    894     Parser.Lex();
    895 
    896     if (Parser.getTok().isNot(AsmToken::Colon)) {
    897       Error(Parser.getTok().getLoc(), "unexpected token");
    898       return MatchOperand_ParseFail;
    899     }
    900     Parser.Lex();
    901 
    902     if (Parser.getTok().isNot(AsmToken::Identifier)) {
    903       Error(Parser.getTok().getLoc(), "unexpected token");
    904       return MatchOperand_ParseFail;
    905     }
    906 
    907     StringRef Identifier = Parser.getTok().getString();
    908     Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
    909                                   Kind, Ctx);
    910     Parser.Lex();
    911   }
    912 
    913   SMLoc EndLoc =
    914     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
    915 
    916   if (AllowTLS)
    917     Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
    918                                                     StartLoc, EndLoc));
    919   else
    920     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
    921 
    922   return MatchOperand_Success;
    923 }
    924 
    925 // Force static initialization.
    926 extern "C" void LLVMInitializeSystemZAsmParser() {
    927   RegisterMCAsmParser<SystemZAsmParser> X(TheSystemZTarget);
    928 }
    929