/toolchain/binutils/binutils-2.25/gas/testsuite/gas/ppc/ |
476.s | 100 divw 10,11,12 101 divw. 11,12,13
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a2.s | 118 divw. 20,21,22 119 divw 20,21,22
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476.d | 107 184: (7d 4b 63 d6|d6 63 4b 7d) divw r10,r11,r12 108 188: (7d 6c 6b d7|d7 6b 6c 7d) divw\. r11,r12,r13
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a2.d | 143 1cc: (7e 95 b3 d7|d7 b3 95 7e) divw\. r20,r21,r22 144 1d0: (7e 95 b3 d6|d6 b3 95 7e) divw r20,r21,r22
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/external/valgrind/none/tests/ppc32/ |
jm-int.stdout.exp | 42 divw 00000000, 000f423f => 00000000 (00000000 00000000) 43 divw 00000000, ffffffff => 00000000 (00000000 00000000) 44 divw 000f423f, 000f423f => 00000001 (00000000 00000000) 45 divw 000f423f, ffffffff => fff0bdc1 (00000000 00000000) 46 divw ffffffff, 000f423f => 00000000 (00000000 00000000) 47 divw ffffffff, ffffffff => 00000001 (00000000 00000000) 191 divw. 00000000, 000f423f => 00000000 (20000000 00000000) 192 divw. 00000000, ffffffff => 00000000 (20000000 00000000) 193 divw. 000f423f, 000f423f => 00000001 (40000000 00000000) 194 divw. 000f423f, ffffffff => fff0bdc1 (80000000 00000000 [all...] |
/external/llvm/test/MC/PowerPC/ |
ppc64-encoding.s | 419 # CHECK-BE: divw 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd6] 420 # CHECK-LE: divw 2, 3, 4 # encoding: [0xd6,0x23,0x43,0x7c] 421 divw 2, 3, 4 422 # CHECK-BE: divw. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd7] 423 # CHECK-LE: divw. 2, 3, 4 # encoding: [0xd7,0x23,0x43,0x7c] 424 divw. 2, 3, 4 [all...] |
/external/v8/src/ppc/ |
disasm-ppc.cc | 733 case DIVW: { 734 Format(instr, "divw'o'. 'rt, 'ra, 'rb"); [all...] |
assembler-ppc.h | 835 void divw(Register dst, Register src1, Register src2, OEBit o = LeaveOE, [all...] |
macro-assembler-ppc.h | 104 #define Div divw [all...] |
assembler-ppc.cc | 930 void Assembler::divw(Register dst, Register src1, Register src2, OEBit o, function in class:v8::internal::Assembler 932 xo_form(EXT2 | DIVW, dst, src1, src2, o, r); [all...] |
/external/v8/src/compiler/ppc/ |
code-generator-ppc.cc | [all...] |
/external/valgrind/none/tests/ppc64/ |
jm-int.stdout.exp | 42 divw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) 43 divw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) 44 divw 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000) 45 divw 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000) 46 divw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000) 47 divw ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000) 271 divw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) 272 divw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) 273 divw. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000) 274 divw. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000 [all...] |
/external/v8/src/crankshaft/ppc/ |
lithium-codegen-ppc.cc | 970 __ divw(scratch, left_reg, right_reg, SetOE, SetRC); 978 // Check for kMinInt % -1, divw will return undefined, which is not what we [all...] |
/external/valgrind/none/tests/x86/ |
insn_basic.def | 431 divw dx.uw[464] ax.uw[58794] : r16.uw[12345] => ax.uw[2468] dx.uw[38] 432 divw dx.uw[464] ax.uw[58794] : m16.uw[12345] => ax.uw[2468] dx.uw[38] [all...] |
/external/mesa3d/src/mesa/x86/ |
assyntax.h | 431 #define DIV_W(a) CHOICE(divw a, divw a, div a) [all...] |
/external/llvm/test/MC/X86/ |
x86-32-coverage.s | [all...] |